PIPELINE SYNCHRONIZATION Search Results

AD9639

Abstract: s31 schottky diode mdac s29 proportional controller 2812 AN-827 AN-835 JESD204 Packaging Top Mark LFCSP AD9516 generic JESD204 radar
Contextual Info: Quad, 12-Bit, 170 MSPS/210 MSPS Serial Output 1.8 V ADC AD9639 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9639 VIN + A VIN – A BUF SHA BUF SHA BUF SHA BUF SHA DOUT + A PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC 12 VCM A VIN + B

6462D

Abstract: AD9239BCPZ-210 AN-835
Contextual Info: Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC AD9239 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9239 VIN + A VIN – A BUF SHA PIPELINE ADC 12 BUF SHA PIPELINE ADC 12 BUF SHA PIPELINE ADC 12 BUF SHA PIPELINE ADC 12 VCM A VIN + B

ADT1-1WT-1

Abstract: AD9239BCPZ-210 AN-835
Contextual Info: Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC AD9239 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9239 VIN + A VIN – A BUF SHA PIPELINE ADC 12 BUF SHA PIPELINE ADC 12 BUF SHA PIPELINE ADC 12 BUF SHA PIPELINE ADC 12 VCM A VIN + B

D8AB EQUIVALENT

Abstract: d6ab JESD25-5 D4CD
Contextual Info: Quad IF Receiver AD6657 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DRGND AD6657 VIN+A PIPELINE ADC VIN–A 14 NOISE SHAPING REQUANTIZER PIPELINE ADC VIN–B 14 NOISE SHAPING REQUANTIZER 11 VCMB VIN+C PIPELINE ADC VIN–C 14 NOISE SHAPING REQUANTIZER DC0±AB

AD951x

Contextual Info: Quad IF Receiver AD6657A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND AD6657A VIN+A PIPELINE ADC VIN–A 14 NOISE SHAPING REQUANTIZER DO±AB VCMA VIN+B PIPELINE ADC VIN–B 14 NOISE SHAPING REQUANTIZER 11 VCMB VIN+C PIPELINE ADC VIN–C

max9291

Abstract: AD6643-200 CP-64-4 901MH AN83-5 10-com 1401M 10True
Contextual Info: Dual IF Receiver AD6643 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0±

AN-877 ANALOG DEVICES

Contextual Info: Dual IF Receiver AD6643 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0± D10± OEB

Contextual Info: 80 MHz Bandwidth, Dual IF Receiver AD6673 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND AD6673 VIN+A VIN–A PIPELINE 11-BIT ADC JESD-204B INTERFACE NSR VCM VIN+B VIN–B PIPELINE 11-BIT ADC HIGH SPEED SERIALIZERS CLOCK GENERATION

Contextual Info: Dual IF Receiver AD6643 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0±

E19 CORE TRANSFORMER

Abstract: CP-48-1 AD9524
Contextual Info: 80 MHz Bandwidth, Dual IF Receiver AD6673 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND AD6673 VIN+A VIN–A PIPELINE 11-BIT ADC JESD-204B INTERFACE NSR VCM VIN+B VIN–B SYSREF± SYNCINB± CLK± RFCLK PIPELINE 11-BIT ADC HIGH

AD9250

Abstract: E19 CORE TRANSFORMER AD9524 upstream docsis cmts JESD204B
Contextual Info: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9250 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD AGND DGND DRGND AD9250 VIN+A VIN–A PIPELINE 14-BIT ADC VCM VIN+B VIN–B PIPELINE 14-BIT ADC JESD-204B INTERFACE SERDOUT0± CML, TX

WIDEBAND ULTRASOUND

Abstract: JESD204A CP-48-8
Contextual Info: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual Serial Output Analog-to-Digital Converter ADC AD9644 FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD9644 VIN+A VIN–A PIPELINE 14-BIT ADC 14 VCMA VIN+B VIN–B PIPELINE 14-BIT ADC 14 VCMB REFERENCE PDWN SERIAL PORT (SPI)

diode T35 12H

Abstract: 100NS PQFP144 ST10F167 ST10F167 Controller disassembler st10 Bootstrap
Contextual Info: ST10F167 16-BIT MCU WITH 128KBYTE FLASH MEMORY • HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE. – 16-BIT CPU WITH 4 STAGE PIPELINE – 100NS INSTRUCTION CYCLE TIME AT 20MHz CPU CLOCK – 500NS MULTIPLICATION 16*16 BIT – 1µS DIVISION (32/16 BIT)

968dB

Contextual Info: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual Serial Output Analog-to-Digital Converter ADC AD9644 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD9644 VIN+A VIN–A PIPELINE 14-BIT ADC 14 VCMA VIN+B VIN–B PIPELINE 14-BIT ADC 14 VCMB REFERENCE PDWN SERIAL PORT

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET PRELIMINARY 32-bit Proprietary Microcontroller CMOS FR60Lite MB91270/280 Series MB91V280/F272S/F272 • DESCRIPTION ■ FEATURES • FR CPU characteristics • 32-bit RISC, load/store architecture with a five-stage pipeline

Contextual Info: RISCore RISC CPU PROCESSOR PRELIMINARY IDT79R3500A Integrated Device Technology, Inc. FEATURES: • A single chip integrating the R3000 CPU and R3010 FPA execution units, using the R3000A pinout. • Efficient Pipelining— The CPU's 5-stage pipeline design

Contextual Info: November 1996 Micro Linear ML4532, ML4533, ML4536 ^ Servo Burst Area Detector GENERAL DESCRIPTION FEATURES The ML4532 and ML4533 Area Detectors are designed to minimize the pipeline transport delay while accurately quantizing the area of servo bursts in high­

st4848

Abstract: AD7678 AD7678ACP AD7678ACPRL AD7678AST AD7678ASTRL CP-48
Contextual Info: PRELIMINARY TECHNICAL DATA a 18-Bit,100kSPSSARADC AD7678 Preliminary Technical Data FEATURES 18 Bits Resolution with No Missing Codes No Pipeline Delay SAR architecture Differential Input Range: ؎5V Throughput: 100 kSPS INL: ؎2.5 LSB Max (؎9.5 ppm of Full-Scale)

CCL-HL832HS

Abstract: intel strataflash j3 PXA263 278639 EME-G770 HL832HS PXA250 and PXA210 manual PXA262 PXA26x PXA210
Contextual Info: Intel PXA26x Processor Family Electrical, Mechanical, and Thermal Specification Data Sheet Product Features • ■ ■ ■ ■ ■ ■ ■ High-Performance Processor — Intel® XScale Microarchitecture — 7 stage pipeline — 32 KB instruction cache

PXA271

Abstract: PXA272 FND COMMON CATHODE DISPLAY PXA270 jtag flash programming PXA27x core developers guide MCX 90 motorola blackberry mobile phone circuit diagram 0.65mm pitch BGA socket motorola MCX 90 radio PXA272 jtag flash programming
Contextual Info: Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance processor: — Intel XScale® microarchitecture with Intel® Wireless MMX Technology — 7 Stage pipeline

Contextual Info: July 1992 PRELIMINARY Micro Linear ML4532> ML4533, ML4536 Servo Burst Area Detector GENERAL DESCRIPTION FEATURES The ML4532 and ML4533 Area Detectors are designed to m inimize the pipeline transport delay while accurately quantizing the area of servo bursts in high­

The PowerPC Microprocessor Family

Abstract: MPC823
Contextual Info: SECTION 6 THE POWERPC CORE 6.1 FEATURES The following is a list of the core’s main features: • 32-bit PowerPC Architecture • Single-Issue Integer Machine • Variable Pipeline Depth Architecture Tailored to Instruction Complexity • Fully Static Design

Contextual Info: PRELIMINARY TECHNICAL DATA a 18-Bit,570kSPSSARADC AD7679 Preliminary Technical Data FEATURES 18 Bits Resolution with No Missing Codes No Pipeline Delay SAR architecture Differential Input Range: ؎5V Throughput: 570 kSPS INL: ؎2.5 LSB Max (؎9.5 ppm of Full-Scale)

tag 87

Abstract: ATF697FF EB 203 D AT697 ATF280F AT697F PCI analogic device power 23MFLOPS ATF697FF-ZA-E 0x8000004C
Contextual Info: ATF697FF Rad- hard 32 bit SPARC V8 Reconfigurable Processor DATASHEET Features • SPARC V8 High Performance Low-power 32-bit processor core • AT697F Sparc v8 processor • LEON2-FT 1.0.9.16.1 compliant • 8 Register Windows • Advanced Architecture 5 Stage Pipeline