PIN FUNCTION OF IC 317 Search Results

Contextual Info: Preliminary ill# ICW 0RKS WB1332X Dual Serial Input PLL with 1.2GHz and 510MHz Prescalers Features Figure 1 • IC WORKS BiCMOS process Pin Diagram • Operating voltage 2.7V to 5.5V — LI Vcc2 • Operating frequency to 1,2GHz and 510MHz with inputs of - 1 5dBm and Vcc of 3.0V

Contextual Info: Preliminary WB1337X ill# ICW 0RKS Dual Serial Input PLL with 550MHz Prescalers Features Figure 1 IC W O R KS BiCMOS process Pin Diagram Operating voltage 2.7V to 5.5V v cc2 v cc1 Operating frequency to 550M H zw ith inputs of -2 5 d B m and VCC of 3.0V V P2

Contextual Info: m Q u ic k S w itc h P ro d u c ts H ig h - S p e e d S em iconductor,Inc. C M O S B u s -E x c h a n g e 1 8 ' B it q s 316209 Q S3162209 S w itc h FEATURES/BENEFITS DESCRIPTION • The QS316209 provides a set of eighteen high­ speed C M O S T T L -c o m p a tib le b u s-e xch a n g e

Contextual Info: , INC._ PEEL 20CG10-25 CMOS Programmable Electrically Erasable Logic Device Features Advanced CMOS EEPROM Technology High Performance, Low Power Consumption — tp D = 25ns, fmax= 33.3MHz — Ice = 55mA + 0.5mA/MHz

ix 3368

Contextual Info: LOE D • fi235bDS DD5020J 752 « S I E G SIEMENS SIEMENS AKTIENGESELLSCHAF T '< ¿ > 5 - 's Dimmer IC SLB 0586 CMOS 1C Features • Sensor operation - no mechanically moved switching elements • Operation is also possible from several extensions by means of sensors or push buttons

Contextual Info: ICS1574 Integrated Circuit Systems, Inc. User Programmable Laser Engine Pixel Clock Generator Description Features The ICS1574 is a very high performance monolithic phaselocked loop PLL frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed­

Ap1c-d

Abstract: B2379 82378ZB
Contextual Info: intei 82378ZB SYSTEM I/O SIO AND 82379AB SYSTEM I/O APIC (SIO.A) Provides the Bridge Between the PCI Bus and ISA Bus 100% PCI and ISA Compatible — PCI and ISA Master/Slave Interface — Directly Drives 10 PCI Loads and 6 ISA Slots — PCI at 25 MHz and 33 MHz

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping IDT723613 6 4 x 3 6 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge

Contextual Info: ISSI IS61NW6432 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE ADVANCE INFORMATION JULY 1998 FEATURES DESCRIPTION • Fast access time: The IS61NW6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, 'no-wait' bus, secondary cache for the Pentium,

Contextual Info: in te i 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz