PHY REGISTER Search Results

MB87Q3140

Abstract: XAUI link ip 10gbps serdes CX4 cable ethernet chip switch
Contextual Info: 12-Port 10Gbps Ethernet Switch Chip – MB87Q3140 XAUI/CX4 PHY MAC Filter/Lookup MAC PHY XAUI/CX4 MAC PHY XAUI/CX4 MAC PHY XAUI/CX4 On-Chip XAUI/CX4 PHY MAC Shared Filter/Lookup Memory XAUI/CX4 PHY MAC Filter/Lookup Buffer Management MAC/VLAN Table Table Maintenance

PMC-940212

Abstract: 94021
Contextual Info: TM SCI-PHY LEVEL 2 APPLICATION NOTE PMC-940212 ISSUE 4 SATURN-COMPATIBLE INTERFACE FOR ATM PHY DEVICES SCI-PHY SATURN COMPATIBLE INTERFACE SPECIFICATION FOR PHY LAYER AND ATM LAYER DEVICES, LEVEL 2 APPLICATION NOTE ISSUE 4: AUGUST 1997 PMC-Sierra, Inc.

vp 2725

Abstract: FW801BF FW801BF-09-DB S100 S200 S400
Contextual Info: Data Sheet January 2005 FW801BF Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device Distinguishing Features „ „ „ „ ™ „ Supports PHY pinging and remote PHY access packets. „ Fully supports suspend/resume. „ Supports PHY-link interface initialization and reset.

AR7400

Abstract: AR1500 AFE LINE DRIVER RD7400-GE Atheros homeplug reference homeplug av ieee 1901 OFDM powerline transceiver PLC coupling OFDM AR7400 AR1500
Contextual Info: AR7400 IEEE 1901 compliant HomePlug AV MAC/PHY Transceiver Solution Highlights • Supports up to 500 Mbps PHY rates over powerline and 700 Mbps PHY rates over coax • Highly integrated MAC/PHY transceiver, supporting MII and RGMII interfaces • Support for low power EuP directive

td 6316

Abstract: bel s558 LAN83C185 S558-5999-46 CRS100 LAN83C180 LAN91C110 LT1086
Contextual Info: AN 10.13 Migrating from the LAN83C180 10/100 PHY to the LAN83C185 10/100 PHY 1 Introduction This application note discusses how to migrate from an existing design using the SMSC LAN83C180 PHY to SMSC's next generation LAN83C185 PHY. A general overview is provided which includes such

TD 6316

Abstract: LAN83C185 12 pin rj45 with integrated LED 12 pin RJ45 LED 12 pin rj45 connector customer reference board BEL S558-5999-46 RJ45 low connector pcb board CRS100 LAN83C183
Contextual Info: AN 13.9 Migrating from the LAN83C183 10/100 PHY to the LAN83C185 10/100 PHY 1 Introduction This application note discusses how to migrate from an existing design using the SMSC LAN83C183 PHY to SMSC's next generation LAN83C185 PHY. A general overview is provided which includes such

Contextual Info: ISI-220 BIST USB PHY Core BIST for Mixed-signal USB PHY The USB PHY is a Mixed-signal Core that includes both the Digital and Analog blocks of the USB Transceiver Macro-cell UTMI/ UTMI+ Specifications. Testing of the digital section of the PHY is usually accomplished using well known

NanoNET PHY and MAC

Abstract: nanoNET system specifications transistor DA 3309 nanoNET NanoNET PHY and MAC System Specifications nanotron 60870-5-1 CRC Chirp Spread Spectrum Nanotron Technologies 802.15.4a
Contextual Info: nanoNET PHY and MAC System Specifications Version 1.04 NA-03-0101-230-1.04 Document Information nanoNET PHY and MAC System Specifications Document Information Document Title: nanoNET PHY and MAC System Specifications Document Version: 1.04 Released yyyy-mm-dd :

PC MOTHERBOARD chip

Abstract: afe 1000 laptop adapter block diagram laptop motherboard PCB diagram HW2000 PIN DIAGRAM OF RJ11 PIN DIAGRAM OF RJ45 to usb china phone BLOCK diagram electrical home wiring home automation block diagram
Contextual Info: Preliminary Product Brief August 2000 HW3000M/HW2000 Home WireTM Home Phoneline Networking Physical Layer PHY Features • Highly integrated home phoneline networking physical layer PHY solution with 802.3u-compatible media independent interface (MII): — HW3000M HomePNA* PHY

RTL code for ethernet

Abstract: 100BASE-FX LINK100 PHY-100 fiber optic schematic symbols LED latch "LED latch"
Contextual Info: Ethernet PHY-110 Core Preliminary Datasheet The LSI Logic PHY-110 core is a complete physical layer solution for 10 and 100 Mbits/s Ethernet connections. Figure 1 shows a typical application of the PHY-110. When combined with a 10/100 Mbits/s Media Access Controller MAC , the PHY-100 and MAC become a complete

FW802C

Abstract: L-FW802C-DB sony firewire faults FW802C-DB S100 S200 S400
Contextual Info: Data Sheet January 2005 FW802C Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Distinguishing Features ™ „ Supports connection debounce. „ Supports multispeed packet concatenation. „ Supports PHY pinging and remote PHY access packets.

Gigabit Ethernet MAC phy

Abstract: Gate level simulation ethernet mac Ethernet to FIFO FIFO Generator User Guide
Contextual Info: Stratix II GX Embedded Gigabit Ethernet MAC / PHY User's Guide Version 1.0 - October 2005 Stratix II GX Embedded Gigabit Ethernet MAC / PHY User's Guide 1 Stratix II GX Embedded Gigabit Ethernet MAC / PHY User's Guide Version 1.0 - October 2005 Contents 1

prng

Abstract: 77V106 IDT77V106 IDT77V106L25 PE-67583 TLA-6M103
Contextual Info: IDT77V106L25 3.3V ATM PHY for 25.6 and 51.2 Mbps Features ! ! ! ! ! ! ! ! ! ! ! ! ! Description Performs the PHY-Transmission Convergence TC and Physical Media Dependent (PMD) Sublayer functions of the Physical Layer Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5

MIPI spec

Abstract: MIPI DSI spec MIPI csi MIPI DSI u723 MSO9000A DSO9404A DSI mipi mipi mipi d-phy
Contextual Info: Agilent Technologies U7238A MIPI D-PHY Compliance Test Software for Infiniium Oscilloscopes Data Sheet Validate and debug your embedded D-PHY data links quickly and easily Agilent Technologies’ U7238A MIPI D-PHY compliance test software for Infiniium oscilloscopes

frame by vhdl

Abstract: Gate level simulation Gate level simulation without timing Gigabit Ethernet MAC phy Ethernet to FIFO Ethernet-MAC using vhdl serdes
Contextual Info: Stratix II GX Embedded Gigabit Ethernet MAC / PHY User's Guide Version 1.0 - October 2005 Stratix II GX Embedded Gigabit Ethernet MAC / PHY User's Guide 1 Stratix II GX Embedded Gigabit Ethernet MAC / PHY User's Guide Version 1.0 - October 2005 Contents 1

DO-DI-PL42FB4

Abstract: PASSPORT
Contextual Info: Xilinx IP Center POS-PHY Level 4 to Flexbus 4 Bridge Lounge Registration | Silicon Solutions | Design Resources | Services | Documentation | Home : Products & Services : Intellectual Property : Registration - POS-PHY Level 4 to Flexbus 4 Bridge Registration - POS-PHY Level 4 to Flexbus 4 Bridge

Contextual Info: Product Brief November 2005 FW323 NV129 1394a PCI PHY/Link Open Host Controller Interface Features „ 1394a-2000 OHCI link and PHY core function in a single device: — Single-chip link and PHY enables smaller, simpler, more efficient motherboard and add-in card

77V106

Abstract: 77V107 ATM25 IDT77V107 PE-67583 TLA-6M103
Contextual Info: IDT77V107 Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2 Features List ! ! ! ! ! ! ! ! ! ! ! ! Performs the PHY-Transmission Convergence TC and Physical Media Dependent (PMD) Sublayer functions of the Physical Layer Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5

DMX chip

Abstract: DMX single chip controller STS-192 STS-48 VSC9142
Contextual Info: SONET/SDH IP/ATM Framer and Mapper VSC9142 Framers and Mappers Product Brief Features: System / Packet Interface • 32-bit Industry Compliant POS-PHY-3, Single-PHY Packet Interface • 32-bit Industry Compliant UTOPIA-3, Single-PHY Cell Interface Physical Layer Channelization

implement motorola bts

Abstract: NPIS64
Contextual Info: Fact Sheet Freescale Semiconductor, Inc. M-2 UTOPIA / POS-PHY ADAPTER REFERENCE DESIGN Freescale Semiconductor, Inc. PRELIMINARY FEATURES • Adapts the C-3e and C-5e Network Processor interfaces to support single-PHY and multiPHY Utopia and POS-PHY L2, 16 bit interfaces

AD27

Abstract: IP100 100BASE-FX "network interface cards"
Contextual Info: IP100 Integrated 10/100 Ethernet MAC + PHY 1 Features Single chip 10/100BASE, half or full duplex Ethernet Media Access Controller IEEE 802.3 compliant 100BASE-TX PHY IEEE 802.3 compliant 10BASE-T PHY IEEE 802.3 full duplex flow control IEEE 802.3 compliant 100BASE-FX PCS

BCM5241

Abstract: et1100 design guide et1100 VT6103F teridian ET1200 Application Note PHY Selection Guide 2.0 ethercat et1100 vt6303l KSZ8001L
Contextual Info: Application Note Slave Controller PHY Selection Guide Requirements to Ethernet PHYs used for EtherCAT Ethernet PHY Examples Version 1.5 Date: 2009-07-16 1BDOCUMENT HISTORY DOCUMENT HISTORY Version 1.1pre 1.2 1.3 1.4 1.5 Comment First preliminary release • Ethernet PHY requirements revised e.g., link loss reaction time

Contextual Info: POS-PHY Level 4 MegaCore Function Errata Sheet March 2007, MegaCore Version 7.0 This document addresses known errata and documentation issues for the POS-PHY Level 4 MegaCore function version 7.0. Errata are functional defects or errors, which may cause the POS-PHY Level 4 MegaCore

fw843

Abstract: AGERE fw843 L-FW430-07-T144-DB AGERE 1394 fw843 Datasheets FW430 161-ball FW802B
Contextual Info: FW430 07 1394a/b PCI PHY/Link Open Host Controller Interface Product Brief Features „ „ „ „ „ 1394a-2000 OHCI link and PHY core function in a single device: — Single-chip link and PHY enables smaller, simpler, more efficient motherboard and add-in card