PHASE SHIFT DETECTOR Search Results

TEA1007

Abstract: 1007 ignition triac control circuit diagram telefunken 1007 vinax
Contextual Info: Tem ic TEA1007 S e m i c o n d u c t o r s Simple Phase-Control Circuit Description The integrated circuit TEA 1007 is designed as a general phase-control circuit in bipolar technology. It has an internal supply voltage limitation. With typical 150 mA ignition pulse, it is possible to determine the phase shift

PLL CD4046 application

Abstract: VCO cd4046 CD4046 application demodulator PLL cd4046 CD4046 vco application note CD4046 application note 74HC4046 application note metal detector diagram loop 74hc4046 fairchild CD4046
Contextual Info: I R S E M I C C D N D U C T O R C H I L D pPr" 1!,9! Revised April 1999 I 'M Phase Comparator I is an exclusive OR XOR gate. It pro­ vides a digital error signal that maintains a 90 phase shift between the VCO’s center frequency and the input signal (50% duty cycle input waveforms). This phase detector is

EP4SGX70

Abstract: EP4S100G4 EP4SE230 EP4SGX180 EP4S40G2 EP4SGX360
Contextual Info: 5. Clock Networks and PLLs in Stratix IV Devices SIV51005-3.1 This chapter describes the hierarchical clock networks and phase-locked loops PLLs which have advanced features in Stratix IV devices. It includes details about the ability to reconfigure the PLL counter clock frequency and phase shift in real time,

injection

Abstract: AUDIO AMPLIFIER SCHEMATIC
Contextual Info: FEATURES PIN CONFIGURATION • HIGH SENSITIVITY—INPUT LIMITING VOLTAGE AT 4.5 MHz = 400fiV • HIGH IF VOLTAGE GAIN—60dB • SIMPLIFIED TUNING—ONE RLC PHASE SHIFT NETWORK • HIGH STABILITY • LOW DISTORTION—1.0% • WIDE FREQUENCY CAPABILITY—5kHz

Contextual Info: PRELIMINARY V.23/V.21 Single Chip Modem GENERAL DESCRIPTION PIN ASSIGNMENT The XR-2321 is a single-chip asynchronous continuous phase FSK Frequency Shift Keying mode modem. Half or full duplex operation is possible over general switched network or leased line conditions. Modem

sda2120

Abstract: fm operational amplifier
Contextual Info: 120 MHz PLL for AM/FM Receivers o 'l A SDA2120 DIP 22 The SDA 2120 contains the complete digital section reference oscillator, 20-bit shift register with memory, programmable divider, band select outputs as well as a phase detector, two charge pumps, one current multiplier, and two amplifiers for tuning an AM/FM receiver

mip 0253

Abstract: 33R3750
Contextual Info: ABRIDGED VERSION AJ sm m svskm s A TDK G ro u p /C o m p a n y SSI 33P3701 8-48 Mbit/s Magneto Optical Read Channel with PPM/PWM Pulse Qualification Advance Information February 1996 DESCRIPTION PULSE DETECTOR The SSI 33P3701 device is a high performance BiCMOS single chip read channel IC that contains all

Contextual Info: Philips Semiconductors Product specification Low power FM IF system NE/SA614A DESCRIPTION PIN CONFIGURATION The NE/SA614A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength

NE604AN

Abstract: Signal mixing NE602 NE604 SA604A equivalent NE602 equivalent SA604A NE602 NE604AD NE602 equivalent circuit SA604
Contextual Info: Philips Semiconductors Product specification High performance low power FM IF system DESCRIPTION NE/SA604A PIN CONFIGURATION The NE/SA604A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength

U2531

Abstract: U2531B KD201
Contextual Info: ABRIDGED VERSION A B SSI 34P3201 Pulse Detector & Data Synchronizer, 250K to 8.0 Mbit/s c im n iM tm A TDK Group/Company Preliminary Data December 1993 DESCRIPTION FEATURES Highly Integrated Pulse Detector & Data Synchronizer The SSI 34P3201 is a high performance pulse detector

Contextual Info: SSI 34P3200 wconsiiskms' Pulse Detector & Data Synchronizer for High Density Floppy Storage A TDK Group f Company Advance Information January 1993 DESCRIPTION FEATURES The SSI 34P3200 is a high performance pulse detector and data synchronizer integrated circuit. This device is

Contextual Info: COMPUTING AND N E T WO RKI N G GA1085 Figure 1. Block Diagram FBIN S1 R EFC LK SO I T T I f T Ò I |~ 9 ~ | f s l TT TEST E F1 FO |~ T | m GND [~5 VDD Phase Detector VDD 13 QO GND Q1 Q2 Q10 E E EE Phase Select VCO 3 09 11-Output Configurable Clock Buffer GND

CAPACITOR Series EGC

Abstract: floppy read write amplifier
Contextual Info: SSI 34P3200 ¿mmsiistm A TDK Group/Company Pulse Detector & Data Synchronizer for High Density Floppy Storage Preliminary Data December 1993 FEATURES DESCRIPTION The SSI 34P3200 is a high performance pulse detector and data synchronizer integrated circuit. This device is

KZQ 55 - 12

Abstract: TD415 32P5482
Contextual Info: SSI 32P5482 jim s y s k m Pulse Detector & Data Synchronizer s * A TDK Group/Company September 1993 DESCRIPTION FEATURES The SSI 32P5482 is a low power, high performance Pulse Detection, Data Synchronization combination device. This device is designed for use in low power

GA1085

Abstract: GA1085-MC1000
Contextual Info: R I Q U I N T S E M I C O N D U C T O R, I N C . GA1085 Figure 1. Block Diagram FBIN S1 REFCLK S0 F1 F0 GND 11 10 9 8 7 6 5 TEST 12 4 VDD Phase Detector VDD 13 Phase Select VCO Q0 14 MUX GND 15 Q1 16 Q2 17 VDD 18 Q10 2 Q9 1 GND Divide Logic ÷4, ÷5, or ÷6

PA216

Abstract: 42C22 in160
Contextual Info: SSI 34P553/5531 c m m M fa n Pulse Detector & Data Synchronizer s A T D K G ro u p /C o m p a n y December 1993 DESCRIPTION FEATURES The SSI 34P553/5531 is a low power, high performance Pulse Detection, Data Synchronization combination device. This device is designed for use in low power

SA602A

Contextual Info: SA614A Low power FM IF system Rev. 4 — 14 February 2014 Product data sheet 1. General description The SA614A is an improved monolithic low-power FM IF system. It incorporates two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic

3 phase inverters circuit diagram

Abstract: circuit diagram of analog clock using logic gates 3 phase ac inverters circuit diagram CD2545 powr supply Circuit Block Diagram Dflipflops phase detector GHDD4414
Contextual Info: Oki Semiconductor GHDD4414_ Decision Circuit with Phase Detectors GENERAL DESCRIPTION Oki's GHDD4414 is a 10-GHz decision circuit designed to strip data from high-speed serial bit streams in 10-Gbps communication links. Using a clock input at up to 10 GHz and using D-flip-flops, EX-ORs, and

Contextual Info: PHASE DETECTORS PHASE SHIFTERS Surface Mount ❏ Plug-In & Coaxial HIGH OUTPUT 1000 mV DC output, 1 to 400 MHz 180° VOLTAGE VARIABLE SURFACE MOUNT Plug-In & Surface Mount ❏ 8 to 1000 MHz SURFACE MOUNT MPD SYPD MODEL NO. Mini-Circuits RPD ZRPD SPH JSPHS

mcl mpd-2

Contextual Info: PHASE DETECTORS Surface Mount o Plug-In & Coaxial HIGH OUTPUT 1000 mV DC output, 1 to 400 MHz SURFACE MOUNT MPD SYPD MODEL NO. RPD ZRPD FREQUENCY POWER SCALE IMPEDANCE ISOLATION OUTPUT MHz IN ohms FACTOR (dB) POLARITY output RF1 load RF2 RF1 RF1-RF2 RF1/RF2

32F8020

Contextual Info: ju t 1 « * » SSI 32P4722 jilic o n á tík m í' Pulse Detector & Data Separator A TDK Group/Company Advance Information June 1993 DESCRIPTION FEATURES The SSI 32P4722 is a low power, high performance bipolar device that provides pulse detection, data synchronization, and ENDEC electronics on a single

EGC 890

Abstract: KD201 signal detection circuit "peak hold" constant vol Srd 18 vdc
Contextual Info: SSI 34P3201 ¿ itm s u s k m A TDK Group/company s Pulse Detector & Data Synchronizer, 250K to 8.0 Mbit/s Preliminary Data Decem ber 1993 DESCRIPTION FEATURES The SSI 34P3201 is a high perform ance pulse detector and data synchronizer integrated circuit. This device is

Contextual Info: PHASE DETECTORS Surface Mount ❏ Plug-In & Coaxial HIGH OUTPUT 1000 mV DC output, 1 to 400 MHz SURFACE MOUNT MPD SYPD MODEL NO. RPD ZRPD FREQUENCY POWER SCALE IMPEDANCE ISOLATION OUTPUT MHz IN ohms FACTOR (dB) POLARITY output RF1 load RF2 RF1 RF1-RF2 RF1/RF2

c1627

Abstract: c1027 c1627 transistor c1027 transistor c1628 transistor c1026 transistor c1027 c1009 tl431 SO8 C0132
Contextual Info: Application Notes SH 100 G GCDR3300A The GCDR3300A is a macro to be used within the SH100G Gate Array-environment. This macro is designed for 2.5 - 3.3 GHz applications. It contains a 1:2 demultiplexer and a phase detector PD [1] with bit error detection and VCO (fig. 1).