PHASE SHIFT DETECTOR Search Results

DTA 2003 Amp circuit

Abstract: HA16163T TSSOP-20 Full-bridge series resonant converter capasitor 1.2 mf
Contextual Info: HA16163T Synchronous Phase Shift Full-Bridge Control IC REJ03F0001-0300Z Rev.3.00 Apr.21.2003 Features • High frequency operation; oscillator frequency = 2 MHz max. • Full-bridge phase-shift switching circuit with adjustable delay times • Integrated secondary synchronous rectification control with adjustable delay times

TEA1007

Abstract: ignition block diagram TH1 "cross reference" ignition with triac thyristor capacitive discharge ignition triac phase control Triac 12 v cross reference a circuit for firing angle in triac TEA Series triac firing circuit
Contextual Info: TEA1007 Simple Phase Control Circuit Description Integrated circuit, TEA1007, is designed as a general phase control circuit in bipolar technology. It has an internal supply voltage limitation. With typical 150 mA ignition pulse, it is possible to determine the phase-shift

TEA1007

Abstract: 1007 ignition triac control circuit diagram telefunken 1007 vinax
Contextual Info: Tem ic TEA1007 S e m i c o n d u c t o r s Simple Phase-Control Circuit Description The integrated circuit TEA 1007 is designed as a general phase-control circuit in bipolar technology. It has an internal supply voltage limitation. With typical 150 mA ignition pulse, it is possible to determine the phase shift

PLL CD4046 application

Abstract: VCO cd4046 CD4046 application demodulator PLL cd4046 CD4046 vco application note CD4046 application note 74HC4046 application note metal detector diagram loop 74hc4046 fairchild CD4046
Contextual Info: I R S E M I C C D N D U C T O R C H I L D pPr" 1!,9! Revised April 1999 I 'M Phase Comparator I is an exclusive OR XOR gate. It pro­ vides a digital error signal that maintains a 90 phase shift between the VCO’s center frequency and the input signal (50% duty cycle input waveforms). This phase detector is

EP4SGX70

Abstract: EP4S100G4 EP4SE230 EP4SGX180 EP4S40G2 EP4SGX360
Contextual Info: 5. Clock Networks and PLLs in Stratix IV Devices SIV51005-3.1 This chapter describes the hierarchical clock networks and phase-locked loops PLLs which have advanced features in Stratix IV devices. It includes details about the ability to reconfigure the PLL counter clock frequency and phase shift in real time,

EP4CGX150

Abstract: EP4CGX110 EP4CGX30 EP4CE10 EP4CGX15 EP4CGX50 EP4CE6 EP4CGX22 EP4CGX75
Contextual Info: 5. Clock Networks and PLLs in Cyclone IV Devices CYIV-51005-2.1 This chapter describes the hierarchical clock networks and phase-locked loops PLLs with advanced features in the Cyclone IV device family. It includes details about the ability to reconfigure the PLL counter clock frequency and phase shift in real time,

injection

Abstract: AUDIO AMPLIFIER SCHEMATIC
Contextual Info: FEATURES PIN CONFIGURATION • HIGH SENSITIVITY—INPUT LIMITING VOLTAGE AT 4.5 MHz = 400fiV • HIGH IF VOLTAGE GAIN—60dB • SIMPLIFIED TUNING—ONE RLC PHASE SHIFT NETWORK • HIGH STABILITY • LOW DISTORTION—1.0% • WIDE FREQUENCY CAPABILITY—5kHz

ULN2111

Abstract: RDE capacitor
Contextual Info: FEATURES PIN CONFIGURATION • HIGH SENSITIVITY— INPUT LIMITING VOLTAGE AT 4.5 MHz = 400MV • HIGH IF VOLTAGE GAIN— 60dB • SIMPLIFIED TUNING— ONE RLC PHASE SHIFT NETWORK • HIGH STABILITY • LOW DISTORTION— 1.0% • W IDE FREQUENCY CAPABILITY— 5kHz

Contextual Info: PRELIMINARY V.23/V.21 Single Chip Modem GENERAL DESCRIPTION PIN ASSIGNMENT The XR-2321 is a single-chip asynchronous continuous phase FSK Frequency Shift Keying mode modem. Half or full duplex operation is possible over general switched network or leased line conditions. Modem

Contextual Info: TPS61187 www.ti.com SLVSA85D – JUNE 2010 – REVISED FEBRUARY 2012 WLED Driver for Notebooks with PWM Interface and Auto Phase Shift Check for Samples: TPS61187 FEATURES DESCRIPTION • • • • The TPS61187 IC provides a highly integrated WLED driver solution for notebook LCD backlight. This

TPS61187

Contextual Info: TPS61187 SLVSA85C – JUNE 2010 – REVISED SEPTEMBER 2011 www.ti.com WLED Driver for Notebooks with PWM Interface and Auto Phase Shift Check for Samples: TPS61187 FEATURES DESCRIPTION • • • • The TPS61187 IC provides a highly integrated WLED driver solution for notebook LCD backlight. This

sda2120

Abstract: fm operational amplifier
Contextual Info: 120 MHz PLL for AM/FM Receivers o 'l A SDA2120 DIP 22 The SDA 2120 contains the complete digital section reference oscillator, 20-bit shift register with memory, programmable divider, band select outputs as well as a phase detector, two charge pumps, one current multiplier, and two amplifiers for tuning an AM/FM receiver

Contextual Info: TPS61187 www.ti.com SLVSA85D – JUNE 2010 – REVISED FEBRUARY 2012 WLED Driver for Notebooks with PWM Interface and Auto Phase Shift Check for Samples: TPS61187 FEATURES DESCRIPTION • • • • The TPS61187 IC provides a highly integrated WLED driver solution for notebook LCD backlight. This

Scans-008365

Contextual Info: CD < m < m Tl 7J 73 < D I— 73 m I— O O TI Z "0 D O ss _ M CO > ö Q § Q 5§SS VDDIO SCK SDI qnn <— Level Translation Phase Shift Control Bus Access and Registers CSN A1IN A1 IP A1QO 12 go MON DC Null V C C -*MO pJ _ != ^ è = ^ & "ü & ¡s ¡5 5 °

AN969 motorola

Abstract: motorola AN969 Theory and Application of Sampling Phase Detector MC1451XX ZF steering analog phase shift maxim max 1987 AN969 MC12016 MC145159
Contextual Info: M O TO RO LA SEMICONDUCTOR APPLICATION NOTE Â N 969 O p e ra tio n f th e M C I 4 5 1 5 9 PLL F re q u e n c y S y n th e s iz e r w ith Analog P hase D e te c to r IN T R O D U C T IO N As stated earlier, the MC145159 has a sample-and-hold phase detector. As opposed to standard digital phase com­

mip 0253

Abstract: 33R3750
Contextual Info: ABRIDGED VERSION AJ sm m svskm s A TDK G ro u p /C o m p a n y SSI 33P3701 8-48 Mbit/s Magneto Optical Read Channel with PPM/PWM Pulse Qualification Advance Information February 1996 DESCRIPTION PULSE DETECTOR The SSI 33P3701 device is a high performance BiCMOS single chip read channel IC that contains all

Contextual Info: Philips Semiconductors Product specification Low power FM IF system NE/SA614A DESCRIPTION PIN CONFIGURATION The NE/SA614A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength

NE604AN

Abstract: Signal mixing NE602 NE604 SA604A equivalent NE602 equivalent SA604A NE602 NE604AD NE602 equivalent circuit SA604
Contextual Info: Philips Semiconductors Product specification High performance low power FM IF system DESCRIPTION NE/SA604A PIN CONFIGURATION The NE/SA604A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength

Contextual Info: R R series Thermal Emission Microscope IAHEAI New High-sensitivity detector thermal detector InSb Motorized turret with objective lenses • Two objective lenses for analyzing thermal emissions • Three objective lenses for probing and laser scanning Thermal Emission Microscope

KD201

Abstract: AGC AMPLIFIER
Contextual Info: AU ABRIDGED VERSION ¿wmâfàms A TDK G roup/C ro u p /com pany SSI 34P3201 Pulse Detector & Data Synchronizer, 250K to 8.0 Mbit/s P r e l i m i n a r y D a ta December 1993 DESCRIPTION FEATURES Highly Integrated Pulse D etector & Data Synchronizer The SSI 34P3201 is a high performance pulse detector

U2531

Abstract: U2531B KD201
Contextual Info: ABRIDGED VERSION A B SSI 34P3201 Pulse Detector & Data Synchronizer, 250K to 8.0 Mbit/s c im n iM tm A TDK Group/Company Preliminary Data December 1993 DESCRIPTION FEATURES Highly Integrated Pulse Detector & Data Synchronizer The SSI 34P3201 is a high performance pulse detector

Contextual Info: SSI 34P3200 wconsiiskms' Pulse Detector & Data Synchronizer for High Density Floppy Storage A TDK Group f Company Advance Information January 1993 DESCRIPTION FEATURES The SSI 34P3200 is a high performance pulse detector and data synchronizer integrated circuit. This device is

Contextual Info: COMPUTING AND N E T WO RKI N G GA1085 Figure 1. Block Diagram FBIN S1 R EFC LK SO I T T I f T Ò I |~ 9 ~ | f s l TT TEST E F1 FO |~ T | m GND [~5 VDD Phase Detector VDD 13 QO GND Q1 Q2 Q10 E E EE Phase Select VCO 3 09 11-Output Configurable Clock Buffer GND

Contextual Info: /: S // I FO GND G C /v u Figure 1. Block Diagram F B IN TEST VOD QO GND Q1 Q2 VDD S1 SO F1 w 3 Phase Detector VDD 010 Phase Select VCO 09 I L r , i a L 11-Output Configurable Clock Buffer GND Divide Logic +5, or *6 E 08 t4 , Features * Group B 03 27 Output Butters j Gr£up