PECLR Search Results

regenerator in optical

Abstract: GR-253-CORE PM5313 PM5363 STM-16
Contextual Info: PM5313 SPECTRA-622 PMC-Sierra,Inc. SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces ATP[1:0] PREFEN PECLREF • • • • SCPI[3:0] SCPO[1:0] Serial Control Port Path Trace Buffer Rx Telecom Aligner Rx Path O/H Processor Drop Bus PRBS Generator/

GR-253-CORE

Abstract: PM5313 PM5363 STM-16
Contextual Info: PM5313 SPECTRA-622 PMC-Sierra,Inc. SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces ATP[1:0] PREFEN PECLREF • • • • SCPI[3:0] SCPO[1:0] Serial Control Port Path Trace Buffer Rx Telecom Aligner Rx Path O/H Processor Drop Bus PRBS Generator/

GSP2E-7401

Abstract: sirf grf2i GSP2E GSP2e-7400 GSP2E7410 7400 series pin connection grf1/lx grf2i ADC7810 TTL 7410
Contextual Info: This document becomes an UNCONTROLLED COPY once printed from SiRF’s Intranet. To receive a controlled copy, please contact Document Control. SiRF Application Note GSP2e Hardware Implementation Document Number APNT0012 Revision 1.1 5/16/2000 Author: Oded Yossifor

Contextual Info: DEVICE SPECIFICATION B iC M O S PECL C L O C K GENE R ATO R S44Q5 FEATURES APPLICATIONS • Generates six clock outputs from 20 MHz to 80 MHz HFOUT operates from 10 MHz to 40 MHz • Allows PECL or TTL reference input • Provides differential PECL output at up to 160

nrzi to nrz circuit diagram

Abstract: nrzi circuit diagram MLT-3 PE68551 media converter circuit diagram mlt resistor parallel scrambler davicom ethernet 100BASE-FX DM9301 DM9301F
Contextual Info: DM9301 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter General Description The DM9301 is a physical-layer, single-chip, lowpower media converter for 100BASE-TX/FX full duplex repeater applications. On the TX media side, it provides a direct interface to Unshielded Twisted

89HPES24N3

Abstract: 89HPES24N3BXG
Contextual Info: 89HPES24N3 Data Sheet 24-Lane 3-Port PCI Express Switch Device Overview – Supports locked transactions, allowing use with legacy software – Ability to load device configuration from serial EEPROM ◆ Highly Integrated Solution – Requires no external components

ty 612

Abstract: PJ 3139
Contextual Info: PMC-Sierra, Inc. ADVANCE PM5313 SPECTRA-622 DATA SHEET PMC-981162 ISSUE 2 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S PM5313 SPECTRA-622 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S DATA SHEET PROPRIETARY AND CONFIDENTIAL ADVANCE ISSUE 2: MAY 1999

SI 1150H

Abstract: xnxx 1155H 16 x E1 G.703 MP 9720 ds yt 1208 diode 1N311
Contextual Info: PM5313 SPECTRA-622 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S DATA SHEET PRELIMINARY ISSUE 3: OCTOBER 1999 Proprietary and Confidential to PMC-Sierra Inc., and for its Customers’ Internal Use REVISION HISTORY Issue No. Issue Date Details of Change

1N07

Abstract: relay cross reference z570 1062H
Contextual Info: PMC-Sierra, Inc. PRELIMINARY PM5313 SPECTRA-622 DATA SHEET PMC-1981162 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S PM5313 SPECTRA-622 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S DATA SHEET PRELIMINARY ISSUE 4: FEBRUARY 2000 Proprietary and Confidential to PMC-Sierra Inc., and for its Customers’ Internal Use

transistor s3050

Abstract: S3050 R488 TRANSISTOR SUBSTITUTION DATA BOOK capacitor stream resistor 220 TRANSISTOR MMBT3904LT1 S3052 S3057 SDM7128-XC
Contextual Info: Part Number S3057/S3050/S3052 Revision 2.01 - March 26, 2001 Multi-Rate Application Note PRELIMINARY APPLICATION NOTE S3057 Xcvr, S3050 CRU, S3052 PM, and Sumitomo SDM7128-XC Optic Xcvr. INTRODUCTION The AMCC S3057 transceiver chip is a fully integrated serialization/deserialization SONET STS-48/OC-48

TRANSISTOR SUBSTITUTION DATA BOOK

Abstract: s3067 OC-24 S3062 S3078 STS-48 Signal Path Designer
Contextual Info: Part Number S3078, S3067, S3062 Revision 2.01 - March 26, 2001 Multi-Rate APPLICATION NOTE S3078 CRU, S3067 Xcvr, S3062 PM w/FEC and Sumitomo Fiber Optic Xcvr. INTRODUCTION The AMCC S3067 transceiver chip is a fully integrated serialization/deserialization SONET STS-48/OC-48, STS-24/

rdl 117-a

Abstract: pa-1000b
Contextual Info: A d v a n c e d v O .7 ? TM P r o A S IC ^ F la s h F a m ily F P G A s High Performance, Low Skew, Splitable Global Network 100% Routability and Utilization I/O Schmitt-Trigger Option on Every Input Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate

Contextual Info: PRELIMINARY AMDZ1 Am79C730 Integrated Multiport Repeater for 100 Mbps IMR100 DISTINCTIVE CHARACTERISTICS • Fully integrated four-port 100BASE-TX repeater device compatible with IEEE 802.3u specifications ■ Enables the design of systems that meet IEEE

Alter PQFP208

Abstract: p633 PGA391 p626 CPGA391 BGA391 Str720
Contextual Info: STR720 ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES PRODUCT PREVIEW
Memories – 16 KBytes Program RAM Memory – External SDRAM Interface for up to 128 Mbytes SDRAM. – External Memory Interface EMI for up to 8

Contextual Info: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os

schematic diagram online UPS for high frequency

Abstract: ag19
Contextual Info: v3.3 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process

APA750

Abstract: GL25 4kx8 sram
Contextual Info: v3 .4 PLUS ProASIC TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process

RAM256X9SST

Abstract: ProASICPLUS Flash Family FPGAs v5.0
Contextual Info: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os

APA075

Contextual Info: v4.1 ProASICPLUS TM Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os Military and Mil-Std 883B • • • 300, 000 to 1 million System Gates

S3056

Abstract: S3057 SDM7128-XC STS-48 S3052 Signal Path Designer
Contextual Info: Part Number S3057 Revision 1.0 - April 26, 2000 PRELIMINARY APPLICATION NOTE S3057 Transceiver, S3056 CRU, S3052 Performance Monitor, Sumitomo SDM7128-XC Optic Transciever INTRODUCTION The AMCC S3057 transceiver chip is a fully integrated serialization/deserialization SONET STS-48/OC-48 2.488

1kx8 static ram

Contextual Info: v5.1 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os

OB25LPLL

Abstract: diagram LG 21 fs 4 bg model circuits MIL-STD-8831 RAM256X9AA APA075
Contextual Info: v5.5 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os

sklansky adder verilog code

Abstract: vhdl code for 8-bit brentkung adder dadda tree multiplier 8bit dadda tree multiplier 4 bit radix 2 modified booth multiplier code in vhdl 8-bit brentkung adder vhdl code Design of Wallace Tree Multiplier by Sklansky Adder 4 bit multiplication vhdl code using wallace tree vhdl code Wallace tree multiplier 16 bit carry lookahead subtractor vhdl
Contextual Info: SmartGen Cores Reference Guide Hyperlinks in the SmartGen Cores Reference Guide PDF file are DISABLED. Please see the online help included with software to view the content with enabled links. Actel Corporation, Mountain View, CA 94043 2009 Actel Corporation. All rights reserved.

media converter circuit diagram

Abstract: nrzi to nrz converter circuit diagram E1 to fiber optic converter circuit MLT 22 525 V23812 digital clock ckt diagram Tx/Fx Media Converter media converter optical fibre nrzi mlt resistor
Contextual Info: DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter General Description recovery circuits to minimize bit delay through the converter no FIFO is used to buffer data between the FX and TX interfaces . Furthermore, due to the excellent rise/fall time control by a built-in waveshaping filter, the DM9301FP needs no external filter