PECL3 Search Results

PECL

Abstract: PECL3-H 3PECLH 3PECLH-0.5 3PECLH-10 PECL3-10
Contextual Info: 3-Bit Programmable Delay Modules PECL3 Series 10K ECL Logic 3PECLH Series 10KH ECL Logic Delay per Step ns Error ref. to "000" (ns) OUT 16 15 ECL 3-Bit Schematic P2 P3 10 9 3-Bit Programmable Delay Line Output Buffer Available in Surface Mount Electrical Specifications at 25OC

20STEP

Contextual Info: RHOMBUS I N D U S T R I E S 27E » IN C 7724120 0000141 • 1 ■ 10K & 100K ECL BUFFERED DELAY MODULES 3-BIT 10K ECL PROGRAMMABLE THROUGH-HOLE DIL. PECL3-XX SERIES PART NUMBER PECL3-.5 PECL3-1 PECL3-2 PECL3-3 PECL3-4 PECL3-5 PECL3-6

Contextual Info: 3-Bit Programmable Delay Modules PECL3 Series 10K ECL Logic 3PECLH Series 10KH ECL Logic Vcc OUT 16 15 ECL 3-Bit Schematic P2 10 £2 Output Buffer 3-Bit Programmable Delay Line 1_ Available in Surface Mount Vcc P1 IN Vee ENABLE input E , Pin 2, is active low.

Contextual Info: RHOMBUS IN D U S T R IE S INC 45E » IRHB 7 7 B IH 2 0 0000253 1 10K & 100K ECL BUFFERED DELAY MODULES r-V7-/7 3-BIT 10K ECL PROGRAMMABLE THROUGH -HOLE D IL STEP Mn. Max. Max. ns (IW) D«v. (m DELAY (ns) PART NUMBER PECL3-0.5 PECL3-1 PECL3-2 P EC LM PECL3-4

Contextual Info: PECL3 Series 10K ECL Logic 3-Bit Programmable Delay Modules Electrical Specifications at 25°C 3-Bit 10K ECL Part Number Delay per Step ns PECL3-0.5 PECL3-0.75 PECL3-1 PECL3-1.2 PECL3-1.25 PECL3-1.3 PECL3-1.5 PECL3-1.75 PECL3-2 PECL3-2.5 PECL3-3 PECL3-5

D1640-0

Contextual Info: 10K ECL Logic 3-Bit Programmable Delay Modules Part Number Delay per Step ns PECL3-0.5 PECL3-1 PECL3-1.5 PECL3-2 PECL3-2.5 PECL3-3 PECL3-3.5 PECL3-4 PECL3-4.5 PECL3-5 PECL3-10 0.5 ± .25 1.0 ±.40 1.51.50 2.0 ± .70 2.5 ± .70 3.0 ± .70 3.51.80 4.01.80

3PECLH

Abstract: PECL3 3PECLH-0.5 3PECLH-10 PECL3-10
Contextual Info: PECL3 Series 10K ECL Logic 3-Bit Programmable Delay Modules Electrical Specifications at 25OC Error ref. 3-Bit 10K ECL Delay per to 000 Part Number Step ns (ns) PECL3-0.5 0.5 ± .25 ± .30 PECL3-0.75 0.75 ± .3 ± .50 PECL3-1 1.0 ± .4 ± .50 PECL3-1.2 1.2 ± .4

Contextual Info: Electrical Specifications at 25°C Delay Max. Deviation Output Delay ns per Program Setting (P3*P2*P1) per Step ref. to Part Number (ns) (ns) no 4 4.5 5 ±.30 PECL3-0.5 0.5 ±.25 3 ±.30 3.5 5.5 6.5 4 ±.50 PECL3-1 ±.40 3 ±.30 5 7 9 PECL3-1.5 1.5 ±.50

Contextual Info: PECL3 Seríes 10K ECL Logic 3-Bit Programmable Delay Modules Electrical Specifications at 25°C Delay per Step ns Error ref. to 000 (ns) Initial Delay (ns) 000 000 001 010 011 100 101 110 PECL3-0.5 0.5 ± .25 + .30 3 + 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

LVDS register

Contextual Info: CDCE72010 SCAS858C – JUNE 2008 – REVISED JANUARY 2012 www.ti.com Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor Check for Samples: CDCE72010 FEATURES 1 • • • • • • • • • • • • • • High Performance LVPECL, LVDS, LVCMOS

DY6009

Abstract: DY6020 DY6035 DY6055 DynaChip IO258 dy6000-family
Contextual Info: DY6000 Family FAST Field Programmable Gate Array™ Features • • • • • • • • • • • • • • • • • • • • • Predictable, Fast, Patented Active Repeater™ Architecture I/O Data-Transfer Rates up to 200MHz 2.7ns I/O Clock-to-Output Time with 10pf Load;

bob smith termination

Abstract: 557571-1 aui isolation transformer 16T MARKING PIN assignments of UTP cables LXT974 LXT974A LXT974B LXT975 LXT975A
Contextual Info: LXT974/LXT975 Fast Ethernet 10/100 Quad Transceivers Datasheet The LXT974 and LXT975 are four-port PHY Fast Ethernet Transceivers which support IEEE 802.3 physical layer applications at both 10 Mbps and 100 Mbps. They provide all of the active circuitry to interface four 802.3 Media Independent Interface MII compliant controllers to

7 pin dil smps power control ic

Abstract: smps control ic with 6 pin sip 6 PIN SMD IC FOR SMPS 7pin smps IC smps ic smd 8 pin 8 PIN SMD IC FOR SMPS 6 PIN SMD IC FOR SMPS primary smps control ic with 6 pin smd 7pin smps control ic 8pin sip 10k
Contextual Info: June 2001 Founded in 1970, Rhombus Industries Incorporated is a privately owned corporation and a leading designer and manufacturer of transformers and magnetic products. Our headquarters is located in Huntington Beach, California and includes engineering, research

Contextual Info: R H O M BU S I N D U S T R I E S INC t.3E P • 7 7 5 1 15 0 0 0 0 0 ^3 1 517 ■ Electrical Spedfications at 25°C Delay Max. Deviation Output Delay ns per Program Setting (P3*P2*P1) per Step Part Number ref. to 000 (ns) (ns) 000 001 010 O il 100 101 110 111

ph5ad

Abstract: REG0011 LVPECL PH6AD
Contextual Info: CDCE72010 www.ti.com. SCAS858 – JUNE 2008 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

A109D

Abstract: A274D LTC6950
Contextual Info: LTC6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution Description Features Low Phase Noise and Jitter n Additive Jitter: 18fs RMS 12kHz to 20MHz n Additive Jitter: 85fs RMS (10Hz to Nyquist) n EZSync Multichip Clock Edge Synchronization

RGC S-PQFP-N64

Abstract: ph5ad CMOS divider 10 100 1000 CDCE72010 QFN-64 LE 9540
Contextual Info: CDCE72010 www.ti.com. SCAS858 – JUNE 2008 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

Zener 4v7

Abstract: 2 - MHz TTL Level oscilator PM5357 XC1701L 3.1v ZENER DIODE
Contextual Info: PM5357 S/UNI-622-POS ERRATA PMC-2001584 ISSUE 1 S/UNI-622-POS REFERENCE DESIGN ERRATA PM5357 S/UNI-622-POS SATURN USER NETWORK INTERFACE 622-POS REFERENCE DESIGN ERRATA ISSUE 1: DECEMBER 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Contextual Info: CDCE72010 SCAS858C – JUNE 2008 – REVISED JANUARY 2012 www.ti.com Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor Check for Samples: CDCE72010 FEATURES 1 • • • • • • • • • • • • • • High Performance LVPECL, LVDS, LVCMOS

ph5ad

Contextual Info: CDCE72010 www.ti.com. SCAS858 – JUNE 2008 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

CDCE72010

Abstract: QFN-64 REG0009
Contextual Info: CDCE72010 www.ti.com. SCAS858A – JUNE 2008 – REVISED JULY 2009 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

CDCE72010

Abstract: QFN-64
Contextual Info: CDCE72010 www.ti.com. SCAS858 – JUNE 2008 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

RGC S-PQFP-N64

Abstract: LE 9540 CDCE72010 QFN-64
Contextual Info: CDCE72010 www.ti.com. SCAS858A – JUNE 2008 – REVISED JULY 2009 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

E1 to fiber optic converter circuit

Abstract: TXCg 25.0
Contextual Info: IDT77V7101 Gigabit Serdes Transceiver Preliminary Information* HDWXU WXUHV ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ $SSO SSOLFD LFDWLRQV IEEE 802.3z Gigabit Ethernet compatible ANSI X3T11 Fibre Channel compatible 1.25 Gbps full duplex transmission and reception in a single