PASSIVE DELAY LINE 16 PIN 10 TAPS Search Results

Delay Lines

Abstract: SMD 0505 RESISTOR 10K OHMS SMD transistor M05 equivalent ZO 607 TZB12-5 TF80 AMY-5 analog delay line schematic AML1-12-10 PLDM7-2.5
Contextual Info: Rhombus Industries Inc. 2002 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS

Active (Logic Buffered)

Abstract: AML12-1 SP24L10005 SMD transistor M05 AMY-5 LVMDM-45G PLDM7-2.5 SMD 0505 RESISTOR 10K OHMS smd 2d 1002 -reel TZB4* "cross reference"
Contextual Info: Rhombus Industries Inc. 2001 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS

DLM5

Abstract: dlm_tf 2SA1927 TF100-10 TF400-10 TF80 125OC TF100-5 TF120-5 TF150-5
Contextual Info: Fast Rise Time td / tr TF Series Fast tr High Performance 20 Section 10-Tap 28-Pin Delay Lines High Bandwidth 10 0.35 / tr Low Distortion LC Network 10 Equal Delay Taps Standard Impedances: 50 - 75 - 100 - 200 Ω Stable Delay vs. Temperature: 100 ppm/OC

Contextual Info: A LLE N A V IO N IC S, INC. SIP 10 TAPS 14 PIN PASSIVE SIP 5 TAPS 7 PIN PASSIVE SIP 1 TAPS 3 PIN PASSIVE 20P 21P 22P SPECIFICATIONS: • Operating Temperature Range: O’C to +70°C -55°C to +125°C up on request •Storage Temperature Range:-65T to +125"C.

TF50-10

Contextual Info: Fast Rise Time t j t ~ 1 0 TF Series Fast tr High Performance 20 Section 10-Tap 28-Pin Delay Lines High Bandwidth ~ 0.35 / f Low Distortion LC Network 10 Equal Delay Taps Standard Impedances: 50 - 7 5 - 100 - 200 Q. Stable Delay vs. Temperature: 100 ppm PC

2214-120C

Abstract: 2214-200C 2214-300C 2214-400C 2214-40C 2214-500C 2214-600C 2214-80C
Contextual Info: 2214 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 data 3  delay devices, inc. FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN

Contextual Info: 2214 data 3  delay devices, inc. 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN

400d

Contextual Info: 2214 data 3  delay devices, inc. 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN

400d

Abstract: 2214-120C 2214-200C 2214-300C 2214-400C 2214-40C 2214-500C 2214-600C 2214-80C
Contextual Info: 2214 data 3  delay devices, inc. 20-TAP DIP DELAY LINE TD/TR = 10 SERIES 2214 FEATURES • • • • • PACKAGES 20 taps of equal delay increment High bandwidth (TD/TR =10) Low profile Epoxy encapsulated Meets or exceeds MIL-D-23859C N/C 1 24 N/C IN

1519-20A

Abstract: 1519-25A 1519-30A 1519-40A 1519-45A 1519-50A 1519-60A 1519-75A
Contextual Info: 1519 data 3  delay devices, inc. 10-TAP DIP DELAY LINE TD/TR = 5 SERIES 1519 FEATURES • • • • • • PACKAGES 10 taps of equal delay increment Delays as large as 300ns available Low DC resistance Standard 14-pin DIP package Epoxy encapsulated

1519

Contextual Info: 1519 10-TAP DIP DELAY LINE TD/TR = 5 SERIES 1519 FEATURES •      PACKAGES 10 taps of equal delay increment Delays as large as 300ns available Low DC resistance Standard 16-pin DIP package Epoxy encapsulated Meets or exceeds MIL-D-23859C

80P-20051XX

Abstract: 80P-02012XX 80P-02051XX 80P-04012XX 80P-04051XX 80P-06051XX 80P-08012XX 80P-08051XX 80P-10051XX
Contextual Info: Allenavionics 80P Series 24 Pin Dual-In-Lline Series 80P - Passive 24 Pin DIP Delay Line page a-ddl-80p Allenavionics 24 Pin DIP Package Risetime: 10% maximum of total delay see Table1 Characteristic Impedance: 50, 100 & 200 Ohms ±10% 20 Equally Spaced Taps

MIL-STD-454E

Abstract: Military Standard, Test Methods and Procedures fo passive delay line 16 pin 10 taps JBM Electronics L-22-132 F16H
Contextual Info: Military Hi-Reliability QUALITY PROGRAM J B M ' s Q u a l i t y A s s u r a n c e P r o g r a m is d e s i g n e d t o f u l l y c o m p l y w i t h t h e f o l l o w i n g m i l i t a r y s p e c i f i c a t i o n s : 1. MIL-I-45208A 2. MIL-STD-45662 Inspection System Requirements

ATIC 112

Contextual Info: Fast Rise Time td/ t ~ 10 TF Series Fast tr High Performance 20 Section 10-Tap 28-Pin Delay Lines High Bandwidth ~ 0.35 / f Low Distortion LC Network 10 Equal Delay Taps Standard Impedances: 50 - 7 5 - 100 - 200 Q Stable Delay vs. Temperature: 100 ppm/°C

Contextual Info: Electromagnetic Delay Lines Ultra Low Attenuation and Distortion Total Delays up to 1000ns, Fast Rise Times Temperature Stability, 70 ppm/°C Typical. Single, 5 ,1 0 ,1 6 & 20 Tap Standard Configurations Operating Temperature Range: 55 to +125°C Standard Impedances from 50 to 200 Ohms

Contextual Info: • • • • • • • T2L LV CMOS input and outputs Delays stable and precise 8-pin Space Saver package Leads - thru-hole, J, Gull Wing or Tucked Available in delays from 8 to 150ns Output and 2 intermediate taps each isolated and with 12mA output drive capability

uPD9306

Abstract: upd7261 9306A upd9306a harddisk power supply CIRCUIT diagram harddisk schematic
Contextual Info: NEC mPD9306IA CMOS HARD-DISK INTERFACE NEC Electronics Inc. Description Pin Identification The nPD9306 and piPD9306A hard-disk interface HDI chips are unique CM O S single-chip support devices in­ tended for use with the /¿PD7261A hard-disk controller.

L26XX

Abstract: L2671 L-26-116 L-26-115 26160 L-26-67 L26128
Contextual Info: Passive Delay Lines Delay Range 5-450 nsec STYLE L-26 14-pin SIP 10 equally-spaced taps Td/Tr = 5:1 (typ.) For test conditions see page 16. Compatible With Various Logic Systems including TTL and Video Circuits. CONNECTION Total Delay Tolerance = ± 5% or

LPF12A0

Abstract: 5b1c ksd 7400 F585 -32 8116 RAM 1d77 6F12 5a0b x768 BB52
Contextual Info: CXD2728Q Single-Chip Dolby Pro Logic Surround Decoder Preliminary Description The CXD2728Q is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions necessary for Dolby Pro Logic Surround such as an

200ns 10 tap

Contextual Info: A LLEN A V IO N IC S, INC. DIP 24 PIN 20 TAP PASSIVE DELAY LINE 24P SPECIFICATIONS: MECHANIC: Total Delay:20 to 1000 ns Tap Delays:5% increments of total delay Characteristic lmpedance:50 to 200 ohms ± 10% Distoriton: ± 10% max. Temperature Coefficient of Delay: 100 ppm/C max.

analog delay line

Contextual Info: PASSIVE DELAY LINES, SIP PACKAGE RESISTORS CAPACITORS COILS DELAY LINES SP05 SERIES - 7 PIN, 5 TAP SP10 SERIES - 14 PIN, 10 TAP FEATURES Low cost, prompt delivery! Wide variety of values, 5nS to 250nS Precision-grade internal inductor elements ensure excellent stability

Tapped

Abstract: 24DIP-50450 analog delay line
Contextual Info: 24 Pin DIP Tapped Passive Delay Line The 24 Pin DIP Tapped Passive Delay Lines manufactured by Engineered Components Company are designed to provide precise and stable delays for analog delay line applications. These tapped delay lines are provided in a 24-pin DIP package, available in impedances of 50, 100, 200, and 500

ksd 9700

Abstract: 5a0b C400H 4155 cmos 5b1c e32f e729 CXD2728Q krd 1600 65B4
Contextual Info: CXD2728Q Single-Chip Dolby Pro Logic Surround Decoder Description The CXD2728Q is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions necessary for Dolby Pro Logic Surround such as an

ksd 9700

Abstract: CXD2724Q SQC06 SQD15 5b1c ne5522 5A0B CXD2724AQ-1 SQC14 2F18
Contextual Info: CXD2724AQ-1 Single-Chip Dolby Pro Logic Surround Decoder For the availability of this product, please contact the sales office. Description The CXD2724AQ-1 is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions