PARAMETER OF 74ALS20 Search Results

74ALS

Abstract: 74ALS20A 74ALS20AD 74ALS20AN
Contextual Info: 74ALS20A Dual 4-Input NAND Gates Product Specification FUNCTION TABLE A H INPUTS c B H TYPE OUTPUT D TYPICAL SUPPLY CURRENT TOTAL TYPICAL PROPAGATION DELAY 4 .5 ns 7 4A L S 2 0 A 0 .6 5 m A _ I- - V H X H L X H 14-Pin Plastic DIP

74ALS

Abstract: 74ALS20A 74ALS20AD 74ALS20AN 74ALS20 Philips Semiconductors 1996
Contextual Info: INTEGRATED CIRCUITS 74ALS20A Dual 4-Input NAND gate Product specification IC05 Data Handbook Philips Semiconductors 1996 Jul 01 Philips Semiconductors Product specification Dual 4-input NAND gate TYPE 74ALS20A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

Contextual Info: Philips Sem iconductors Product specification Dual 4-input NAND gate TYPE 74ALS20A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 4.5ns 0.65m A 74ALS20A PIN CONFIGURATION ORDERING INFORMATION O RDER CODE DESCRIPTION CO M M E R C IA L RANGE V Cc = 5 V ±10%,

MS-012-AB

Abstract: 74ALS 74ALS20A 74ALS20AD 74ALS20AN SOL-24 TEXTOOL SOCKET DIP16
Contextual Info: 74ALS20A Signetics Dual 4-Input NAND Gates Product Specification ALS Products FUNCTION TABLE INPUTS TYPICAL PROPAGATION DELAY TYPE OUTPUT 4 .5 ns 74A L S 2 0 A TYPICAL SUPPLY CURRENT TOTAL 0 .6 5 mA A B c D Ÿ H H H H L L X X X H X L X X H X X L X H 14-Pin Plastic DIP

Contextual Info: SN74ALS20A, SN74AS20. SN54ALS20A, SN54AS20 DUAL 4-INPUT POSITIVE-NAND GATES D2661. APRIL 1982-REVISED MAY 1986 Package Options Include Plastic ''Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 8NB4AL620A, 8N64AS20

Contextual Info: TO SH IBA TC74VHC20 F/FN/FS/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC20F, TC74VHC20FN, TC74VHC20FS, TC74VHC20FT DUAL 4 -INPUT NAND GATE The TC74VHC20 is an advanced high speed CMOS 4-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

74ALS20

Contextual Info: TOSHIBA TC74VHC20F/FN/FS/FT TOSHIBA CMO S DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC20F, TC74VHC20FN, TC74VHC20FS, TC74VHC20FT DUAL 4 -INPUT NAND GATE The TC74VHC20 is an advanced high speed CMOS 4-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

Contextual Info: TOSHIBA TC74VHC20F/FN/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC20F, TC74VHC20FN, TC74VHC20FT DUAL 4 -INPUT NAND Note The JED EC SOP (FN) is not available in Japan GATE The TC74VHC20 is an advanced high speed CMOS 4-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

74ALS20

Abstract: TC74VHC20F TC74VHC20FN TC74VHC20FS TC74VHC20FT parameter of 74ALS20
Contextual Info: TOSHIBA TC74VHC20F/FN/FS/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC20F, TC74VHC20FN, TC74VHC20FS, TC74VHC20FT DUAL 4 -INPUT NAND GATE The TC74VHC20 is an advanced high speed CMOS 4-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

parameter of 74ALS20

Contextual Info: TO SHIBA TC74VHC20F/FN/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC20F, TC74VHC20FN, TC74VHC20FT DUAL 4 -INPUT NAND Note The JEDEC SOP (FN) is not available in Japan GATE The TC74VHC20 is an advanced high speed CMOS 4-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

parameter of 74ALS20

Abstract: 74ALS20 TC74VHC20F TC74VHC20FN TC74VHC20FT
Contextual Info: TO SH IBA TC74VHC20F/FN/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC20F, TC74VHC20FN, TC74VHC20FT DUAL 4 -INPUT NAND Note The JED EC SOP (FN) is not available in Japan GATE The TC74VHC20 is an advanced high speed CMOS 4-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

74ALS573AD

Abstract: 74als245a 74als561 74ALS131
Contextual Info: M IT S U B IS H I.ALSTTLs M 74A LS 573A P ,c»c9"?” cha«5e- l ^ Y & '- á 7 - 'O S " 91D 12593 ÍDGTL LOGI C DESCRIPTION D PIN CONFIGURATION TOP VIEW) OUTPUT CONTROL INPUT ID FEATURES 3D - E - E - E 5D ~ E 6D -U . - E 2D 2Q - 20 3D 3Q — iz l - 3Q 4D

Contextual Info: 7 N tO * . 7 MITSUBISHI A LSTTLs - 0 5 - D U A L 4 - B IT D - T Y P E E D G E - T R IG G E R E D F L IP - F L O P W IT H 3 - S T A T E O U T P U T IN V E R T E D CDGTL LOGIC) DESCRIPTION The M74ALS876AP is a semiconductor integrated circuit consisting of two 4-bit D-type positive edge-triggered

DT530

Abstract: 74ALS193D 74ALS573AD
Contextual Info: MITSUBISHI ÍDGTL LOGIC} TI D E I bEMTflE? .0012450 S I M ITSUBISHI ALSTTLS 6249827 MITSUBISHI M 7 4 A L S 2 4 0 A P 91D 12458 D CDGTL LOGIC OCTAL B U FFER/LIN E D R IVE R W IT H 3-STATE O U TPUT IN V E R T E D ) 7 ^ 5 5 - 0 DESCRIPTION The M74ALS240AP is a semiconductor Integrated circuit

Contextual Info: MITSUBISHI ALSTTLs M 74A LS1243A P MITSUBISHI iDGTL LOGIC} TI D E | bS4iaa7 DD 15743 4 | Q UADRUPLE BUS TR A N S C E IVE R W IT H 3-STATE O UTPUT N O N IN VER TED /- DESCRIPTION The M74ALS1243AP is a semiconductor integrated circuit consisting of four bus transmitter/receiver circuits with

Contextual Info: MITSUBISHI O G T L 3>EI tiSM^ñS? o o i a s s s 3^f~ LOGIC} MITSUBISHI ALSTTLs M 74A LS533P T = - Ÿ 6 -0 7 -o s * OCTAL D-TYPE TRANSPARENT LATCH W ITH 3-STATE OUTPUT INVERTED 6 2 4 9 82 7 M ITSUBISHI (DGTL LOGIC) DESCRIPTION 9 1D 12 555 D PIN CONFIGURATION (TOP VIEW)

74ALS577

Contextual Info: ’T ^ f& 'O ÿ 'û f MITSUBISHI ALSTTLs M 74ALS577AP OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP W ITH 3 -STATE OUTPUT AND SYNCHRONOUS RESET INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION 9 1D 12607 PIN CONFIGURATION (TOP VIEW) The M74ALS577AP is a semiconductor integrated circuit

D0-15L

Abstract: LS74AD
Contextual Info: 7 z1 % > -'0 '7 -¿ ? S ' M 74ALS873AP ¡C' 3< DUAL 4 -B IT D-TYPE TRANSPARENT LATCH W ITH 3-STATE OUTPUT NONINVERTED 50t° CDGTL LOGIC) DESCRIPTION PIN CONFIGURATION (TOP VIEW) DIR EC T RESET , p " IN P U T I M ° O UTPUT } -q C O N TR O L IN PU T E c

c 2274

Contextual Info: '7 ' '0 7 -0 5 * MITSUBISHI ALSTTLs OCTAL D -TY P E EDGE-TRIGGERED FLIP-FLO P W IT H 3-S TA TE O U TPU T N O N IN V E R TE D . Ä > a 6249827 M IT S U B IS H I (D G TL L O G IC ) DESCRIPTION consisting o f eight D-type positive edge-triggered flipflop circuits w ith 3-state noninverted output and is pro­

Contextual Info: MITSUBISHI ALSTTLs s ti M74ALS564AP OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP W ITH 3-STATE OUTPUT INVERTED 9 1D 12578 6249827 MITSUBISHI <DGTL LOGIC) DESCRIPTION D PIN CONFIGURATION (TOP VIEW) The M74ALS564AP is a semiconductor integrated circuit consisting of eight D-type positive edge-triggered flipflop circuits w ith 3-state Inverted output and Is provided

8 pin dip j k flipflop ic

Abstract: 74ALS08DP
Contextual Info: MITSUBISHI ALSTTLs M 74A LS1640A P MITSUBISHI -CDGTL LOGICi =11 D e I t.54^027 0D157b4 1 OCTAL BUS TR A N SC EIVER W IT H 3-STATE O UTPUT IN V E R T E D T DESCRIPTION The M74ALS1640AP is a semiconductor integrated cir­ cuit consisting of eight bus transmitter/receiver circuits

74ALS131

Abstract: 74ALS573AD
Contextual Info: 7 = ^ ce v -y -0 7 ' -^ S ' MITSUBISHI ALSTTLs M 74ALS874AP .< „c X '8n DUAL 4 -B IT D -T Y P E EDGE-TRIGGERED FLIP-FLO P _ W IT H 3 -S T A T E O U TPU T N O N IN V E R T E D 0249827 MITSUBISHI ÌOGTL LOGIC) DESCRIPTION The M 74ALS874AP Is a sem iconductor integrated circuit

74ALS573AD

Abstract: 74ALS574AD
Contextual Info: M ITSUBISHI ALSTTLs r M 7 4 A L S 1 6 4 5 A P D e | bSMTfla? DDia77T 3 MITSUBISHI -CDGTL LOGIC} OCTAL BUS TR A N SC EIVER W IT H 3-STATE O U TPUT N O N IN VERTED - 7 “' » DESCRIPTION The M74ALS1645AP is a semiconductor integrated cir­ cuit consisting of eight bus transmitter/receiver circuits

m74als

Abstract: M74ALS109AP 74ALS640
Contextual Info: M IT S U B IS H I {D G T l T o G IcT ^ I b H 1 SS? M 6249827 MITSUBISHI 7 4 A CDGTL LOGIC 91D J STTLs L S 1 0 9 A 12 37 4 P D DUAL J-R POSITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T -V & -0 7 - Ô ? DESCRIPTION PIN CONFIGURATION TOP VIEW) The M74ALS109AP is a semiconductor Integrated circuit