PALCE Search Results

gal programming algorithm

Abstract: PALCE29M16 PALCE29M16H PALCE29M16H-25 PD3024
Contextual Info: USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-25 Lattice Semiconductor PALCE29M16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • High-performance semicustom logic ■ Register/Latch Preload permits full logic replacement; Electrically Erasable EE

20V8Q

Abstract: SL06 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PD3024 pal20v8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

22V10B

Abstract: PALC22V10B PALCE22V10 V10B C22V10B C2 2V
Contextual Info: 1P AL C2 2V 10B fax id: 6006 This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs, please refer to the PALCE22V10 PALC22V10B Reprogrammable CMOS PAL Device — Phantom array Features — Top test

6V8L-25LMB

Abstract: CERAMIC LEADLESS CHIP CARRIER 6V8L-15DMB 16v8 programming 16V8-10 PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC PALCE16V8 PALCE16V8-10 PALCE16V8-15 PALCE16V8-25
Contextual Info: PALCE16 V8 CYPRESS Flash Erasable, Reprogrammable CMOS PAL Device • Up to 16 in p u t te rm s and 8 o utp uts Features • 7.5 ns c o m ’l version 5 ns tc o 5 ns ts 7.5 ns t PD 12 5-M H z sta te m ach ine • A c tiv e p ull-up on d ata input pins • Low p o w er version 16V 8L

TEA 2162 AE

Contextual Info: PR E LIM IN A R Y a COM’L Advanced Micro Devices PALCE20RA1 OH-15 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low power at 90 mA Ice ■ 15 ns maximum propagation delay and Programmable replacement for high-speed

Contextual Info: FINAL COM’L: H-7/10/15/20 IND: H-7/10/15/20 PALCE20RA10 Family AduaM nlccero 24-Pin Asynchronous EE CMOS Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • ■ Low pow er at 100 m A Icc ■ TTL-level register preload for testability A s fast as 7.5 ns m axim um propagation delay

htw 323

Abstract: plji palce programming algorithm
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25. Q-20/25 MIL: H-15/20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all GAL 20V8/AS ■ Electrically erasable CMOS technology pro­

AM 16v8

Abstract: palce16v8 programming algorithm PALCE erase AMD PALCE PALCE Programmer palce programming algorithm
Contextual Info: F IN A L COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family AdvaM n,“ o EE CMOS 20-Pin Universal Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity

palce16V8 programming

Abstract: AMD palce16v8 programming palce16v8h20 PALCE16V8Q-25PC palce16v8 programming guide
Contextual Info: _ COM’L: H-10/15/25, Q-15/25 MIL: H-20/25 Cl Advanced Micro Devices PALCE16V8 EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all 20-pln GAL devices ■ Electrically erasable CMOS technology

PALCe22V10D

Abstract: palce22v10 programming guide PALCE22V10H-10E4/BLA PALCE22v10 amd
Contextual Info: C O M ’L: H-10/15/25, Q-25 a MIL: H-10/15/20/25/30 Advanced Micro Devices PALCE22V10 Family 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 10 ns propagation delay and 83.3 M Hz m a x Global asynchronous reset and synchronous

Contextual Info: Ml intpl 6 1992 ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Extensive Software and Programming Support via Intel and Third Party Tools

Contextual Info: COM’L: H-15 ZI Advanced Micro Devices PALCE20RA1 OH-15 24-pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • ■ Programmable replacement for high-speed CMOS orTTL logic TTL-level register preload for testability Easy design with PALASM software

Contextual Info: PALCE16V8HD-15 EE CMOS 24-Pin High-Drive Universal PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • ■ ■ ■ ■ ■ ■ ■ High output-current drive capability 64 mA Iol Programmable Totem-Pole or Open-Draln Outputs 200 mV Hysteresis

16v8h

Abstract: 16V8Q palce16v8 programming algorithm 16v8z PAL16C1 PAL16R8 PALCE16V8 PALCE16V8Z 16V8H-10 16v8z-25
Contextual Info: PALCE16V8 PALCE16V8Z COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/25, Q-20/25 COM’L:-25 IND:-12/15/25 PALCE16V8 and PALCE16V8Z Families EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all 20-pin PAL devices

palce16v8-25pi

Contextual Info: fax id: 6009 PALCE16V8 «f c y p r e s s Flash Erasable, Reprogrammable CMOS PAL Device • QSOP packaging available Features — 7.5 ns com ’l version 5 ns tCo 5 ns ts 7.5 ns tPD 125-MHz state machine • Active pull-up on data input pins • Low power version 16V8L

Contextual Info: PALCE16V8 V CYPRESS Features • • A ctive p u ll-u p on d ata in p u t p in s • Low pow er version 16V 8L • • — 5 5 m A m ax. com m ercial (1 0 ,1 5 ,2 5 n s) — 65 mA max. industrial (1 0 ,1 5 ,2 5 ns) — 65 m A m ilitary (15 an d 25 n s) •

Contextual Info: PALCE22V10 COM'L: H-5/7/10/15/25,0-10/15/25 IND: H-10/15/20/25 PALCE22V10Z COM'L:-25 IND: -15/25 BEYOND PERFO RM A N CE PALCE22V10 and PALCE22V10Z Families 24-Pin EE CMOS Zero Power Versatile PAL Device DISTINCTIVE CHARACTERISTICS ♦ As fast as 5-ns propagation delay and 142.8 MHz fMAX (external)

Contextual Info: s i «»I COM’L PALCE29M16H-25 24-Pin EE CMOS Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • High-performance semicustom logic replacement; Electrically Erasable EE technology allow s reprogrammability ■ 16 bidirectional user-programmable I/O logic

Contextual Info: FINAL COM’L: Q-10 c\ Advanced Micro Devices PALCE22V10Q-10 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • 10 ns propagation delay ■ 83 MHz fMAX external ■ Low-power EE CMOS ■ 10 macrocells programmable as registered or combinatorial, and active high or active low to

palce16v8 programming algorithm

Abstract: AMD palce16v8 programming palce16v8 programming guide palce16v8z pal16r8 programming algorithm APL DOC SIC jmd PROGRAMMER PAL16R8 algorithm amd palce programming Guide palce16v6
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 a MIL: H-15/20/25 Advanced Micro Devices PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all 20-pin GAL devices

20V8

Abstract: 20L8 PALCE20V8
Contextual Info: 20V8 PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL Device Features • QSOP package available — 10, 15, and 25 ns com’l version • Active pull-up on data input pins • Low power version 20V8L — 55 mA max. commercial (15, 25 ns) — 15, and 25 ns military/industrial versions

22v10h

Abstract: 22v10h-5 PALCE22v10 amd pld 22v10h 22v10q 22V10Q-10 PALCE22V10Q
Contextual Info: FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25 PALCE22V10 Family 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 5-ns propagation delay and 142.8 MHz fMAX external ■ Global asynchronous reset and synchronous

22V10B

Abstract: PALC22V10B Cypress Semiconductor PALCE22V10 V10B
Contextual Info: This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs, please refer to the PALCE22V10 PALC22V10B Reprogrammable CMOS PAL Device • Enhanced test features Features — Phantom array • Advanced second generation PAL architecture

EP610

Abstract: PALCE610 CE610H
Contextual Info: FINAL COM’L: H-15/25 PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins