PAL23S8 Search Results

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PAL23S8-20

Contextual Info: COM’L PAL23S8-20/25 Advanced Micro Devices 20-Pin PAI? Device-Based Sequencer DISTINCTIVE CHARACTERISTICS a 14 Registers - 4 Output Logic Macrocells - 4 Output Registers - 6 Buried State Registers • 23 possible array inputs and 8 outputs in a 20-pin

AMPAL23S8

Abstract: AMPAL23S8-20PC 12350-024A
Contextual Info: Cl COM’L Advanced Micro Devices PAL23S8-20/25 20-Pin PAl? Device-Based Sequencer DISTINCTIVE CHARACTERISTICS Individually user-programmable Output Enable OE PTs with polarity control PTs for observing the buried registers on 6 of the output pins Separate PTs for common Synchronous PRESET

PAL29M16

Abstract: PLS105 PLS151 pls103 pls155 AMD PAL18P8 EP1200 PAL18P8 gal programming specification PAL32R16
Contextual Info: MATRA DESIGN SEMICOND 1ÌE D • 53^6455 MAXRA DESIGN SEMIOONDUCTOR d ia lis i b ■ UNIVERSAL LOGIC CIRCUIT ULC (tm) DEVICES i [p ir s D O o ifiiflo m ir ^ 0001037 fln o o ti August 1989 T -^ Z -W -O o i FEATURES Factory-customized pin- and function-compatible replacements for

2272am

Abstract: PAL23S8
Contextual Info: C O M ’L PAL23S8-20/25 Advanced Micro Devices 20-Pin PA1? Device-Based Sequencer DISTINCTIVE C H A R A C T E R IS T IC S • • • • • 14 Registers - 4 Output Logic Macrocells - 4 Output Registers - 6 Buried State Registers 23 possible array inputs and 8 outputs in a 20-pin

AMD socket s1

Contextual Info: AmPAL*23S8 20-Pin IMOX PAL-Based Sequencer AmPAL*23S8 PRELIMINARY DISTINCTIVE CHARACTERISTICS 14 Registers - 4 Output Logic Macrocells OLMs - 4 Output Registers - 6 Buried State Registers (BSRs) 23 possible array inputs and 8 outputs in a 20-pin package

AmPAL23S8-30

Contextual Info: A DV MICRO PLA/PLE/ARRAYS , Tt. D e | 02S7S2t, 0 0 2 7 2 2 7 1 T -V 4 -/3 -V 7 PAL23S8 20-Pin IMOX PAL Device-Based Sequencer Distinctive C haracteristics • • • • • 14 Registers - 4 Output Logic Macrocells OLMs - 4 Output Registers - 6 Buried State Registers (BSRs)

mhs ulc

Abstract: PAL29M16 PLS100 fpla gal programming timing chart PLS101 PLUS405 matra universal logic circuit
Contextual Info: 4 TE D • SflbflMSb 0 0 D 1 D 0 S 73b ■ MMHS MATRA Preliminary llllr iilll I W I n H H l M H S November 1990 OPENASIC DATA SHEET_ UNIVERSAL LOGIC CIRCUIT ULC (tm) DEVICES FEATURES . FACTORY-CUSTOMIZED PIN- AND FUNCTIONCOMPATIBLE REPLACEMENTS FOR FIELDPROGRAMMABLE PAL(tm), GAL(lm), FPLA, AND

PALC16L8Q

Abstract: PAL20RP4B 8Z35 L16R ic 5209 L16L8A 6R6D PALC20L8 pal8l14 PAL10L8
Contextual Info: PAL/PLD D evice Menu STANDBY SPEED tpo in ns (m&) DATA S H E E T P A G E NO. IN PUTS OUTPUTS PRODUCT T E R M S /O U T P U T PAL8L14A PAL6L16A 8 6 14 16 1 1 25 25 90 90 5-141 5-141 PAL10H8 PAL12H6 PAL14H4 PAL16H2 PAL10L8 PAL12L6 PAL14L4 PAL16L2 PAL16C1 10