PACKAGE 48 LCC Search Results

LCC-48C-A01

Abstract: CERAMIC LEADLESS CHIP CARRIER PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC QFN048-C-S560-1
Contextual Info: LEADLESS CHIP CARRIER FUJITSU SEMICONDUCTOR DATA SHEET 48 PAD CERAMIC To Top / Package Lineup / Package Index LCC-48C-A01 EIAJ code :∗QFN048-C-S560-1 48-pad ceramic LCC Lead pitch 40 mil Package width x package length 560 × 560 mil Sealing method Metal seal

Package 48 LCC

Abstract: QFN048-C-S560-1 LCC 48 CERAMIC LEADLESS CHIP CARRIER LCC-48C-A01 PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC 40MIL
Contextual Info: LEADLESS CHIP CARRIER 48 PAD CERAMIC LCC-48C-A01 EIAJ code : ∗QFN048-C-S560-1 Lead pitch 40mil Package width x package length 560 × 560mil Sealing method Metal seal 48-pad ceramic LCC LCC-48C-A01 *Shape of PIN NO.1 INDEX : Subject to change without notice.

SF0048BA02644S

Abstract: DSSF0048BA02644S
Contextual Info: 48 MHz SAW Filter 10 MHz Bandwidth Part Number SF0048BA02644S DESCRIPTION • • • 48 MHz SAW bandpass filter with 10 MHz bandwidth. 10 x 6.5 mm ceramic LCC package. RoHS compliant. TYPICAL PERFORMANCE . 1 . 2 . 3 . 4 . 5 - dB . 6 . 7 . 8 . 9 . 1 . 1 1

DSSF0048BA02645S

Contextual Info: 48 MHz SAW Filter 3.5 MHz Bandwidth Part Number SF0048BA02645S DESCRIPTION • • • 48 MHz SAW bandpass filter with 3.5 MHz bandwidth. 13.3 x 6.5 mm ceramic LCC package. RoHS compliant. TYPICAL PERFORMANCE . . 1 . 2 . 3 . 4 . 5 - dB . 6 . 7 . 8 . 9 z H

SF1575BA02534S

Abstract: marking SB
Contextual Info: 1575.42 MHz SAW Filter 48 MHz Bandwidth Part Number SF1575BA02534S DESCRIPTION • • • 1575.42 MHz SAW bandpass filter with a 48 MHz bandwidth for GPS applications. 2 x 1.6 mm LCC package, 4 pads. RoHS compliant. TYPICAL PERFORMANCE Amp 10 dB/div Amp 1 dB/div

Contextual Info: 48 MHz SAW Filter 10 MHz Bandwidth Part Number SF0048BA02644S DESCRIPTION • • • 48 MHz SAW bandpass filter with 10 MHz bandwidth. 13.3 x 6.5 mm ceramic LCC package, 12 pads. RoHS compliant. TYPICAL PERFORMANCE . 1 . 2 . 3 . 4 . 5 . 6 - dB . 7 . 8 . 9

Contextual Info: SLC-25-7-2-XXX Optical SONET OC-48/SDH STM-16 SFF LC 2x5 Transceiver - 2.488GBaud - +3.3V " PR EL IM IN AR Y Features ! 2.488 Gbps SONET/SDH OC-48 Compliant ! Compliant to Bellcore GR-253 and ITU-T G.957 specification. ! Die Cast Metal Package ! 100Ω differential AC coupled CML PECL Interoperable

68-JLCC package

Abstract: LUPA-1300 LUPA-300
Contextual Info: PRELIMINARY CYIL1SM0300AA-QBC LUPA-300 CMOS Image Sensor 80 MHz pixel rate. It is housed in a 48-pin ceramic LCC package. The sensor is available in a Monochrome version or Bayer RGB patterned color filter array Applications • • Machine vision Motion tracking

Contextual Info: a FEATURES 80 M Hz Pipelined Operation Triple 10-Bit D/ A Converters RS-343A/ RS-170 Compatible Outputs TTL Compatible Inputs +5 V CM OS M onolithic Construction 40-Pin DIP Package ADV7121 44-Pin PLCC Package (ADV7122) 48-Lead TQFP (ADV7122) CMOS 80 MHz, Triple 10-Bit Video DACs

Contextual Info: Preliminary CMOS SRAM KM68FS2000Z, KM68FR2000Z Family Document Title 256Kx8 SUper Low Power and Low Voltage Full CMOS SRAM Data Sheets for 48-CSP Revision History Rev No. History Draft Data Remark Rev. 0.0 - 1 st edition - Package Dimension Finalized Feb. 6 th, 1997

Contextual Info: KM616V4010C, KM616U4010C Family CMOS SRAM 256Kx16 bit Low Power and Low Voltage CMOS Static RAM with 48-CSP Chip Scale Package Revision No. 0.0 0.01 0.1 1.0 Draft Date Remark I nitial draft - UB/LB power control Errata correction July 4, 1998 Preliminary

Contextual Info: Preliminary CMOS SRAM KM68FS1000Z, KM68FR1000Z Family Document Titie 128Kx8 Super Low Power and Low Voltage Full CMOS SRAM Data Sheets for 48-CSP Revision History Rev. No. History Draft Data Rem ark Rev. 0.0 - 1 st edition - Package Dimension Finalized Feb. 6 th, 1997

Contextual Info: HD7 4 LVC16240A 16-bit Buffers / Line Drivers with 3-state Outputs HITACHI Description The HD74LVC16240A has sixteen inverter drivers with three state outputs in a 48 pin package. This device is a inverting buffer and has two active low enables 1G to 4G . Each enable independently

Contextual Info: Preliminary CMOS SRAM KM616FS1000Z, KM616FR1000Z Family Document Titie 64Kx16 SUper Low Power and Low Voltage Full CMOS SRAM Data Sheets for 48-CSP Revision History Rev. No. History Draft Data Rem ark Rev. 0.0 - 1 st edition - Package Dimension Finalized Feb. 4 th , 1 9 9 7

Contextual Info: HD74LVC16241 16-bit Buffers / Line Drivers with 3-state Outputs HITACHI Description The HD74LVC16241 has sixteen buffer drivers with three state outputs in a 48 pin package. This device is a non inverting buffer and has two active low enables 1G, 4G , high enables (2G, 3G). Each enable

29F800TA

Abstract: 29f800ba MBM29F800 29F800T
Contextual Info: • FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP I (Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type)

Contextual Info: HD74LVC16241-16-bit Buffers I Line Drivers with 3-state Outputs Description The HD74LVC16241 has sixteen buffer drivers with three state outputs in a 48 pin package. This device is a non inverting buffer and has two active low enables 1G, 4G , high enables (2G, 3G). Each enable

Contextual Info: DISTINCTIVE CHARACTERISTICS • Single 3.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard word-wide pinouts 48-pin TSOP Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type

Contextual Info: HD7 4 LVC16244A 16-bit Buffers / Line Drivers with 3-state Outputs HITACHI Description The HD74LVC16244A has sixteen line drivers with three state outputs in a 48 pin package. This device is a non inverting buffer and has two active low enables 1G to 4G . Each enable independently controls

Contextual Info: HD74LVC16374A 16-bit D-type Flip Flops with 3-state Outputs HITACHI Description The HD74LVC16374A has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up reguirements, are transferred to the Q outputs on positive

Contextual Info: FLASHMEMORY CMOS • FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type

Contextual Info: HD74LVC16373A 16-bit D-type Transparent Latches with 3-state Outputs HITACHI Description The HD74LVC16373A has sixteen D type latches with three state outputs in a 48 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data

Contextual Info: HD74LVC16373A-16-bit D-type Transparent Latches with 3-state Outputs Description The HD74LVC16373A has sixteen D type latches with three state outputs in a 48 pin package. When the latch enable input is high, the Q outputs w ill follow the D inputs. When die latch enable goes low, data at

Contextual Info: H D 74L V C 16374A — 16-bit D-type Flip Flops with 3-state Outputs Description The HD74LVC16374A has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up reguirements, are transferred to the Q outputs on positive