P90C401 Search Results
P90C401 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
toshiba tlc 711
Abstract: a815c MCU90-9 tlcs-90 cpu 230890 DO41113 IC 74hcxx QFP64-P-1420A AOI gate d flip flop mcu90
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OCR Scan |
p90c400/401tmp90c400n/tmp90c401tmp90c400f/tmp90c401tmp90c400+14 | |
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Contextual Info: T O SH IBA 3.5 TMP90C400/401 Function of Ports The TM P90C400 contains a total of 56 pins TM P90C401:38pins input/output ports. These ports function not only for the general-purpose I/O but also for the input/output of the in ternal CPU and I/O. Table 3.5 describes the functions of these ports. |
OCR Scan |
tmp90c400/401p90c400p90c40138pins+1 | |
R211D
Abstract: P5SC z3ps
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OCR Scan |
tlcs-90p90c400n/tmp90c401np90c400f/tm+7 | |
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Contextual Info: TO SH IBA TM P90C400/401 3.1.2 EXF Exchange Flag For TM P90C400, “E X F ” , which is inverted when the command “E X X ” is executed to tran sfer d ata between the m ain register and the au x iliary register, is allocated to the first bit of memory address FF8FH . |
OCR Scan |
p90c400/401p90c400mcu90-10ff20h+3 | |
PC RAM
Abstract: ZP15A Z1P31 mcu90 Z1P35 tmp90c ZP40C
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OCR Scan |
tmp90c400tmp90c400n/tmp90c401ntmp90c400f/tmp90c401ftmp90c401+8 | |
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Contextual Info: TMP90C400/401 TO SH IBA 3.4.2 IDLE 1 Mode Figure 3.4 3 shows the tim ing for releasin g the h alt state by interrupts in the IDLE 1 mode. In the ID LE 1 mode, only the internal oscillator and the watchdog tim er operate. The system clock in the MCU stops, and the C L K sign al is fixed at the “ 1” . |
OCR Scan |
tmp90c400/401p60-p67p90c401p90c400+1 | |
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Contextual Info: TO SH IBA 3.2 TMP90C400/401 M em ory Map The TM P90C400 supports a program memory and a d ata memory of up to 60K bytes. The program and d ata memory may be assign ed to the address space from 0000H to FFFFH . 1 Internal ROM The TM P90C400 internally contains a 4K-byte ROM. The address space from 0000H |
OCR Scan |
tmp90c400/401p90c4000000h0010h+2 |