P1B7 Search Results

AD9755

Abstract: AD9755AST AD9755ASTRL AD9755-EB P1B10 MHz VCO C0225
Contextual Info: FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 71 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

detector c band

Abstract: AD9773 AD9773BSV AD9773EB P1B10 SV-80
Contextual Info: 12-Bit, 160 MSPS 2؋/4؋/8؋ Interpolating Dual TxDAC+ D/A Converter AD9773* FEATURES 12-Bit Resolution, 160 MSPS/400 MSPS Input/Output Data Rate Selectable 2؋/4؋/8؋ Interpolating Filter Programmable Channel Gain and Offset Adjustment f S/4, fS/8 Digital Quadrature Modulation Capability

k1404

Abstract: transistor k1404 remote control tx-2b TX-2B RX-2B rx 2b DML4 DML4 Calibration tx-2b equivalent RX-2B TX-2B RX-2B, TX-2B
Contextual Info: Preliminary Data Sheet November 2000 T9000 ISDN Network Termination Node NTN Device 1 Description • The T9000 is an ISDN network termination node device that is highly integrated and provides a lowcost solution to support the following: General-purpose I/O (GPIO) ports with interrupt

AD9753

Abstract: AD9753AST AD9753ASTRL AD9753-EB P1B10 Opt pam circuit
Contextual Info: 12-Bit, 300 MSPS High Speed TxDAC+ D/A Converter AD9753* APPLICATIONS Communications: LMDS, LMCS, MMDS Base Stations Digital Synthesis QAM and OFDM GENERAL DESCRIPTION The AD9753 is a dual, muxed port, ultrahigh speed, singlechannel, 12-bit CMOS DAC. It integrates a high quality 12-bit

Contextual Info: Digital I/O PCI-7396 96-CH High-Driving DIO Card Introduction The PCI-7396 is 96-bit parallel digital input/output DIO cards designed for industrial applications. The PCI-7396 emulates four 8255 Programmable Peripheral Interface (PPI) chips. Each PPI offers three 8-bit DIO ports which can be

DSP56ADC16

Abstract: 56adc16 bba 3rd sem datasheet ADS96002 VMEbus interface handbook 80286 microprocessor schematics architecture of microprocessor 80386 adc16s BBA 1st sem date sheet DSP96000
Contextual Info: Motorola Digital Signal Processors DSP96002 Interface Techniques and Examples by MOTOROLA R. Z. O. A. Robles Rozenshein Rubinstein Vainberg APR10 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of

Contextual Info: a APPLICATIONS Communications: LMDS, LMCS, MMDS Basestations Digital Synthesis Quadrature Modulation LATCH DVDD LATCH PORT1 PORT2 CLK+ CLKCLKVDD PLLVDD CLKCOM DCOM The AD9751 has been optimized for ultra high speed applications up to 300MSPS where data rates exceed

QDAC

Abstract: AD9777BSV P1B14 P2B15
Contextual Info: PRELIMINARY TECHNICAL DATA 16-Bit 160 MSPS 2x/4×/8× Interpolating Dual TxDAC+ D/A Converter a AD9777 Preliminary Technical Data APPLICATIONS FEATURES 16 Bit Resolution, 160 MSPS Conversion Rate Selectable 2×/4×/8× Interpolating Filter Programmable Channel Gain and Offset Adjustment

Contextual Info: PRELIMINARY TECHNICAL DATA 16-Bit, 160 MSPS TxDAC+ with 2x/4×/8× Interpolation and Signal Processing a AD9786 Preliminary Technical Data FEATURES PRODUCT DESCRIPTION 16-Bit Resolution, 160 MSPS Input Data Rate Selectable 2×/4×/8× Interpolating Filters

k1404

Abstract: B2DN remote control tx-2b tx 2b TX-2B Transmitter GPD040 GPD210
Contextual Info: Advance Data Sheet April 2000 T9000 ISDN Network Termination Node NTN Device 1 Description • The T9000 is an ISDN network termination node device that is highly integrated and provides a lowcost solution to support the following: General-purpose I/O (GPIO) ports with interrupt

Contextual Info: FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 71 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

Contextual Info: FEATURES 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 64 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

AD9751

Abstract: 3310D 31B12 AD9751AST AD9751ASTRL AD9751-EB AWG2021 DG2020 HP8644
Contextual Info: FEATURES 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 64 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

AD-009

Abstract: 4CX12 AD009 P1B7 SQ801 28A28
Contextual Info: a 12-Bit, 160 MSPS 2؋/4؋/8؋ Interpolating Dual TxDAC+ D/A Converter AD9773* FEATURES 12-Bit Resolution, 160/400 MSPS Input/Output Data Rate Selectable 2؋/4؋/8؋ Interpolating Filter Programmable Channel Gain and Offset Adjustment f S/4, fS/8 Digital Quadrature Modulation

10358

Abstract: AD9782 P1B10 on-semiconductor data
Contextual Info: 12-Bit, 200 MSPS/500 MSPS TxDAC+ with 2x/4×/8× Interpolation and Signal Processing AD9782 Preliminary Technical Data FEATURES PRODUCT DESCRIPTION 12-bit resolution, 200 MSPS input data rate Selectable 2×/4×/8× interpolation filters Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes

100-6 p86

Abstract: TQFP80 footprint dimensions db sub9 epm7128atc MW2X3C TTL 7452 P2E4 QFP80 12KR1 TQFP80
Contextual Info: ST90158-EMU2B HDS2V2 EMULATOR USER MANUAL 1 PREAMBLE This user manual describes the emulator configurations from the hardware point of view. For topics completely related to software part of the tool, refer to the WGDB9+ Getting Started Manual or on-line help. The following sections are documented in the WGDB9+ Getting

IC 74ls32

Abstract: intel 8086 microprocessor LT 7220 8086 microprocessor kit manual IC 74LS74 BPK72 BPK-70 IC746 IC820 3103* intel
Contextual Info: in te T APPLICATION NOTE AP-119 December 1982 ORDER NUMBER: 310367-002 6-15 AP-119 characteristics of the BPK 72 and is intended to further ease the design effort required in the im­ plem entation of bubble mem ory systems. INTRODUCTION To date, a m ajor obstacle in the im plem entation of

AD8345

Abstract: AD9777
Contextual Info: 16-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter AD9777 FEATURES Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V

P1B00

Abstract: Flat Ribbon Connector 2x10 IDC Female 16 QAM Transmitter block diagram 1b07 SEV 1011 AD9751 AD9751AST AD9751ASTRL AD9751-EB AWG2021
Contextual Info: FEATURES 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 64 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

relay 12v dc 5 chan

Abstract: P2B4 100M RELAY p2b5 IDO26 P1A4 DI815 IDI56 IDO10 IDO24
Contextual Info: Digital I/O Modules Isolated digital communication is one of the most common requirements of a production test system because of the need to communicate with handlers, binning equipment, and user controls. Keithley’s digital I/O modules can also interact

U5-121

Abstract: P1B14 10358 AD9786 IS136 P1B10 operational amplifier 10358 48 TQFP-EP 25VQ
Contextual Info: 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2x/4×/8× Interpolation and Signal Processing AD9786 FEATURES PRODUCT DESCRIPTION 16-bit resolution, 200 MSPS input data rate IMD 90 dBc @10 MHz Noise spectral density NSD : −164 dBm/Hz @ 10 MHz WCDMA ACLR = 80 dBc @ 40 MHz IF

AD9751

Abstract: AD9751AST AD9751-EB AWG2021 DG2020 HP8644 ofdm equations 8075an
Contextual Info: FEATURES 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output: 64 dB Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 V Supply Operation

P1D8

Abstract: AD9777 AD9777BSV AD9777EB SV-80
Contextual Info: 16-Bit, 160 MSPS 2؋/4؋/8؋ Interpolating Dual TxDAC+ D/A Converter AD9777* FEATURES 16-Bit Resolution, 160 MSPS/400 MSPS Input/Output Data Rate Selectable 2؋/4؋/8؋ Interpolating Filter Programmable Channel Gain and Offset Adjustment f S/4, fS/8 Digital Quadrature Modulation Capability

Contextual Info: 10-Bit, 300 MSPS High Speed TxDAC+” D/A Converter AD9751 Preliminary Technical Data ANALOG ► DEVICES 7-1-99 FEATURES DVDD 10-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD: 75 dB Internal 2x Clock Doubler/PLL Differential or Single Ended Clock Input