P1213 Search Results

89H48T12G2

Contextual Info: 48-Lane 12-Port PCIe Gen2 System Interconnect Switch 89HPES48T12G2 Data Sheet ® Device Overview The 89HPES48T12G2 is a member of the IDT PRECISE family of PCI Express® switching solutions. The PES48T12G2 is a 48-lane, 12port system interconnect switch optimized for PCI Express Gen2 packet

89H64H16G3

Abstract: PES64H16G3 89HPES64H16G3
Contextual Info: 64-Lane 16-Port PCIe Gen3 System Interconnect Switch 89HPES64H16G3 Data Sheet ® Device Overview – Autonomous and software managed link width and speed control – Per lane SerDes configuration • Full back channel equalization support • Rx, 5 tap DFE

zilog z8p

Contextual Info: P r e l im in a r y P r o d u c t S p e c if ic a t io n Z86C33/C43 CMOS Z8 MCU C onsumer C o n tr o ller P ro cesso r FEATURES Device ROM KB RAM* (Bytes) Speed (MHz) 32 Input/Output Lines (C43) 24 Input/Output Lines (C33) Z86C33 Z86C43 4 4 237 236 12, 16

L43C

Contextual Info: P r e l im in a r y C u s t o m e r P r o c u r e m e n t S p e c if ic a t io n Z86L33/L43 C o nsum er C ontroller P rocessor FEATURES RAM* Bytes I/O Lines Voltage Range • Device ROM (KB) Vectored, Polarity Prioritized Interrupts with Programmable Z86L33

Contextual Info: P r e l im in a r y C u s t o m e r P r o c u r e m e n t S p e c if ic a t io n Z86C30/C31 /C32/C40 C M O S Z8 C o n s u m e r Contro ller Pr o c e sso r FEA T U R ES Part ROM K B RAM* (Byte) Speed (MHz) 4 2 2 4 237 125 237 236 16 12 12 16 Z86C30 Z86C31

Z8609

Contextual Info: P r e l im in a r y P r o d u c t S p e c if ic a t io n COPY ONLY FEB 2 6 1998 Z86093 NO UPDATE ROM less CMOS 8-B it 28 MCU FEATURES RAM* Bytes Speed (MHz) • Device ROM (KB) Two Programmable 8 -Bit Counter/Timers, Each with Two 6 -Bit Programmable Prescaler

nt5cc64m

Contextual Info: 1Gb DDR3 SDRAM F-Die NT5CB C 128M8FN / NT5CB(C)64M16FP Options Features  Differential clock input (CK, ) Speeds  Differential bidirectional data strobe  DDR3 - 1866  TDQS and /TDQS pair for X8  DDR3/DDR3L/DDR3L RS - 1600  8n-bit prefetch architecture

PES48H12G2

Abstract: 89H48H12G2
Contextual Info: 48-Lane 12-Port PCIe Gen2 System Interconnect Switch ® Device Overview The 89HPES48H12G2 is a member of the IDT PRECISE family of PCI Express® switching solutions. The PES48H12G2 is a 48-lane, 12port system interconnect switch optimized for PCI Express Gen2 packet

Z86C30

Abstract: Z86C31 Z86C32 Z86C40
Contextual Info: Z86C30/C31/C32/C40 CP96DZ82900 ZILOG PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z86C30/C31/C32/C40 CMOS Z8 CONSUMER CONTROLLER PROCESSOR FEATURES • 32 Input/Output Lines C40 24 Input/Output Lines (C3X) ■ Vectored, Prioritized Interrupts with Programmable Polarity

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

Contextual Info: 64-Lane 16-Port PCIe Gen3 System Interconnect Switch 89HPES64H16G3 Data Sheet ® Device Overview – Autonomous and software managed link width and speed control – Per lane SerDes configuration • Full back channel equalization support • Rx, 5 tap DFE

TMS320C40

Abstract: P3A7 TMX320C40GFL TM320C UY13-UY20 2532 eprom texas LCSR HM6208 transistor P3d SPRU035
Contextual Info: TMS320C4x Parallel Processing Development System Technical Reference 1993 Digital Signal Processing Products Printed in U.S.A., August 1993 2576298-9761 revision C SPRU075A Volume # Book Type Two Lines Book Type Volume # Book Type Two Lines Book Type Title

Contextual Info: 64-Lane 16-Port PCIe Gen3 System Interconnect Switch 89HPES64H16G3 Data Sheet ® Device Overview – Autonomous and software managed link width and speed control – Per lane SerDes configuration • Full back channel equalization support • Rx, 5 tap DFE

Contextual Info: 64-Lane 16-Port PCIe Gen2 System Interconnect Switch 89HPES64H16G2 Data Sheet ® Devic e Ove r vie w The 89HPES64H16G2 is a member of the IDT PRECISE family of PCI Express® switching solutions. The PES64H16G2 is a 64-lane, 16port system interconnect switch optimized for PCI Express Gen2 packet

89H48H12

Abstract: 89H48H12G3
Contextual Info: 48-Lane 12-Port PCIe Gen3 System Interconnect Switch 89HPES48H12G3 Data Sheet ® Device Overview – Autonomous and software managed link width and speed control – Per lane SerDes configuration • Full back channel equalization support • Rx, 5 tap DFE

PES64H16AG2

Abstract: 89H64H16AG2 89HPES64H16AG2 89H64H16
Contextual Info: 64-Lane 16-Port PCIe Gen2 System Interconnect Switch ® Device Overview The 89HPES64H16AG2 is a member of the IDT PRECISE family of PCI Express® switching solutions. The PES64H16AG2 is a 64-lane, 16-port system interconnect switch optimized for PCI Express Gen2

28F128J3d

Abstract: eia e700 aaab PrPMC8005E-1259 PRPMC800 NCR asic PC16550A ad57 dram he nv PrPMC carrier 001 RISCwatch emerson electric thermocouple
Contextual Info: i PrPMC8005E Processor PMC Module Installation and Use 6806800A42B September 2008 Edition Copyright 2008 Emerson All rights reserved. Trademarks Emerson, Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of

Architecture of TMS320C4X FLOATING POINT PROCESSOR

Abstract: Architecture of TMS320C4X TMS320C4X FLOATING POINT PROCESSOR block diagram block diagram of of TMS320C4X INSTRUCTION SET of TMS320C4X TMS320C4X TMS320C40 TM320C dsp processor Architecture of TMS320C4X TIBPAL16R6
Contextual Info: TMS320C4x Parallel Processing Development System Technical Reference 1993 Digital Signal Processing Products Printed in U.S.A., August 1993 2576298-9761 revision C SPRU075A Book Type Two Lines Volume # Book Type Volume # Book Type Two Lines Title Two Lines

Contextual Info: Z86L33/L43 CP96LV01501 P FB Jm Y C ustom P p o a m m S fs k a m Z86L33/L43 CMOS Z8 C ONSUM ER C O N T R O LL E R PROCESSOR FEATURES • 32 Input/Output Lines L43 24 Input/Output Lines (L33) ■ Vectored, Prioritized Interrupts with Programmable Polarity

Z86L33

Abstract: Z86L43 P0001
Contextual Info: Z86L33/L43 CP96LVO1501 PRELIMINAR Y CUSTOMER P ROCUREMENT S PECIFICA TION Z86L33/L43 CMOS Z8 CONSUMER CONTROLLER PROCESSOR FEATURES Part Z86L33 Z86L43 ROM KB 4 4 RAM* (Bytes) 237 236 Speed (MHz) 8 8 • 32 Input/Output Lines (L43) 24 Input/Output Lines (L33)

Contextual Info: 48-Lane 12-Port PCIe Gen2 System Interconnect Switch 89HPES48H12G2 Data Sheet ® Devic e Ove r vie w The 89HPES48H12G2 is a member of the IDT PRECISE family of PCI Express® switching solutions. The PES48H12G2 is a 48-lane, 12port system interconnect switch optimized for PCI Express Gen2 packet

PU120

Abstract: P120 1PM12 9112P C78K0R TS016 250LED P150-P153Low
Contextual Info: ・本資料に記載されている内容は2009年1月現在のもので，今後，予告なく変更することがあります。量産設計 の際には最新の個別データ・シート等をご参照ください。 ・文書による当社の事前の承諾なしに本資料の転載複製を禁じます。当社は，本資料の誤りに関し，一切その責

pinout 1156

Abstract: 89HPES64H16 64H16 1156pin
Contextual Info: 89HPES64H16 Data Sheet 64-Lane 16-Port PCI Express System Interconnect Switch ® Device Overview Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin algorithms – Virtual channels arbitration based on priority

Z86C30

Abstract: Z86C31 Z86C32 Z86C40 4 mhz ceramic resonator 3-pin 4243 dm
Contextual Info: Z86C30/C31/C32/C40 CP95DZ81600 CUSTOMER PROCUREMENT SPECIFICATION Z86C30/C31/C32/C40 CMOS Z8 CONSUMER CONTROLLER PROCESSOR FEATURES • 32 Input/Output Lines C40 24 Input/Output Lines (C3X) ■ Vectored, Prioritized Interrupts with Programmable Polarity