OV 9712 Search Results

18v10

Abstract: GAL 18v10 programming Guide
Contextual Info: Lattice Semiconductor Corporation G A L 2 2 V 1 0 F a m ily G AL18V10 G AL22V10 G AL26C V12 ” FEATURES • HIGH PERFORMANCE E ^M O S* TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 50 MHz — TTL Compatible 8 -1 6 mA Outputs — UltraMOS* 111Advanced CMOS Technology

16V8A

Abstract: GAL16V8A GAL programmer schematic 200a liu GAL16VB GAL16VBB aco iad 16v8 16v8b GAL16V8B
Contextual Info: LATTICE SEMICONDUCTOR M7E Lattice D • S a ô b ^ Q00n32 2 HLAT G AL16V8B T-M -l< -01 G A L 1 6 V 8 A High Performance E2CMOS PLD FUNCTIONAL BLOCK DIAGRAM FEATURES >HIGH PERFORMANCE E*CMOS° TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax =100 MHz

GAL16V8A-25LP

Abstract: GAL16V8A-25QP
Contextual Info: Lattice GAL16V8B G A LI6V 8A High Performance E2CMOS PLD FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 1 00 MHz — 5 ns Maximum from Clock Input to Data Output — TTL Compatible 24 mA Output*

Contextual Info: LAT T IC E S E M I C O N D U C T O R bfiE D Lattice S3flbIì4cl 0 0 G 3 0 1 b 173 « L A T GAL20V8/883 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay

gal16v8a

Abstract: gal16v8b PAL gal16v8b GAL16V8A-10LP
Contextual Info: Lattice GAL16V8B GALI 6V8A High Performance E2CMOS PLD FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E’ CMOS» TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 5 ns M aximum from C lock Input to Data O utput — TTL Com patible 24 m A O utputs

gal22v10b

Contextual Info: GAL22V10B GAL22V10 Lattice High Performance E2CMOS PLD FU N C TIO N AL B LO C K DIAG R AM FEATURES >HIGH PERFORMANCE E^CMOS* TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 111 MHz — 5 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs

GAL20ra10

Contextual Info: Lattice Semiconductor G A L 20R A 10 High Performance E2CMOS Generic Array Logic Corporation ™ FEA TU R ES FU N C TIO N A L B LOCK DIA G R A M •HIGH PERFORMANCE E^M O S TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 50 MHz — 15 ns Maximum from Clock Input to Data Output

Contextual Info: Lattice Semiconductor GAL20RA10 High Performance E2CMOS Generic Array Logic Corporation™ FEATURES FUNCTIONAL BLOCK DIAGRAM ypL □ - • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 50 MHz — 15 ns Maximum from Clock Input to Data Output

Contextual Info: Lattice G A L 2 6 C V 1 2 B High Performance E2CMOS PLD Generic Array Logic •■■ FUNCTIONAL BLOCK DIAGRAM FEATURES ¡=53- • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 105 MHz — 7ns Maximum from Clock Input to Data Output

Contextual Info: Lattice GAL20V8A/883 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 15 na Maximum Propagation Delay — Fmax - 50 MHz — 12 na Maximum from Clock Input to Data Output — TTL Compatible 24 mA Output*

MJD31C

Abstract: IPMB POWeR1208P1
Contextual Info: AN INTELLIGENT HOT-SWAP CONTROLLER FOR ATCA FRU A Lattice Semiconductor White Paper April 2005 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: 503 268-8000 www.latticesemi.com 1 An Intelligent Hot-Swap Controller for ATCA FRU

Contextual Info: LAT T IC E S E M I C O N D U C T O R bfiE D Lattice 0 D D 3 G2 4 E4T GAL22V10/883 High Performance E2CMOS PLD Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 62.5 MHz

vas05

Abstract: GAL26CV12-15LP SAAB GAL26CV12 GAL26CV12B block diagram of vas tester
Contextual Info: LA T T I C E S E M I C O N D U C T O R Lattice 47E D • SBflbTMT 0 0 0 5 0 1 2 1 « L A T GAL26CV12B T-M-n-oj GAL26CV12 High Performance E2CMOS PLD FEATURES FUNCTIONAL BLOCK DIAGRAM —O • HIGH PERFORMANCE E2CMOS* TECHNOLOGY — 10 ns Maximum Propagation Delay

Contextual Info: Lattice G A L 2 0 R A 1 0 / 8 8 3 High-Speed Asynchronous E*CMOS PLD Generic Array Logic F U N C T IO N A L B L O C K D IAG RAM FE A TU R E S • HIGH PERFORMANCE E*CM O S* TECHNOLOGY — 20 ns Maximum Propagation Delay — Fmax = 41.7 MHz — 20 ns Maximum from Clock Input to Data Output

Contextual Info: I a tti PP !^ h C I H l W w ispLSI ' 1016/883 in-system programmable Large Scale Integration High-Density Programmable Logic Functional Block D iagram Features • IN-SYSTEM PROGRAM M ABLE HIGH-DENSITY LOGIC — — — — — — M IL-STD-883 Version of th e ispLS11016

Contextual Info: GAL16V8B GAL16V8A Lattice High Performance E2CMOS PLD FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 100 MHz — 5 ns Maximum from Clock Input to Data Output — TTL Compatible 24 mA Outputs

gal20v8a-15lp

Abstract: GAL20V8A-25LP ic tea 1090 GAL20V8A25LP GAL20V8A GAL20V8A15LP 200T1 GAL20V8 LAT 000VIN GAL20V8A-20QJI
Contextual Info: LATTICE SEMICONDUCTOR 4?e i> • 5 3 s t tm ü o o iis t s « lat GAL20V8B GAL20V8A iiiLattice High Performance E^MOS PLD FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS* TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax =100 MHz — 5 ns Maximum from Clock Input to Data Output

AM9709

Abstract: AM97C09 9712c 5009CN 5011CN 97C09 9709a
Contextual Info: Analog Switches/Multiplexers Semiconductor A M 9709/A M 97C 09/A H 5009 Series Monolithic Analog Current Switches General Description A versatile fa m ily o f m o n o lith ic J F E T analog switches designed to e con o m ically f u lf ill a w ide va rie ty o f m u lt i­

Contextual Info: Lattice is p G D S 2 2 / 1 8 / 1 4 in-system programmable Generic Digital Switch Semiconductor Corporation FEATURES FUNCTIONAL BLOCK DIAGRAM ispGDS22 HIGH-SPEED SWITCH MATRIX — 7.5 ns Maximum Propagation Delay — Typical Icc = 25 mA — UltraMOS Advanced CMOS Technology

ne 5555 timer

Abstract: EIA96 MOSFET designer manual PAC-Designer Software LTC4245 POWR1220AT8 EIA-96 abel i2c
Contextual Info: PAC-Designer Software User Manual Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 503 268-8000 July 2010 Copyright Copyright 2010 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied,

1505C

Abstract: 74ABT899 74ABT899A 74ABT899D
Contextual Info: Philips Semiconductors Product specification 9-bit dual latch transceiver with 8-bit parity generator/checker 3-State FEATURES DESCRIPTION • Sym m etrical (A and B bus functions are identical) The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate

Contextual Info: Lattice' | Semiconductor I Corporation ispLSI 5512V In-System Programmable 3.3V SuperWIDE High Density PLD — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Features SuperWIDE™ HIGH-DENSITY IN-SYSTEM

1683K

Abstract: 1683-K
Contextual Info: MSK DWG. NO. REV. SHEET SCALE SIZE 1711-12459 C 1 OF 13 NTS A 8218 Rev J REVISIONS REV. ECO NO. A B C DATE APPROVED RLSD 13329 13808 13884 - 11/30/05 01/23/06 07/11/06 C. HEISELMAN C. HEISELMAN C. HEISELMAN „ G/ÿ/èfe S REVISION REVISION INDEX SHEET c 2

Contextual Info: LATTICE SEMICONDUCTOR •■■ ■■■ 47E D Lattice ■ SBflbTMT O O O n f l O 2 ■ L A T GAL18V10 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES ’ HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15 ns Maximum Propagation Delay