OUI12 Search Results

TQ80223

Abstract: 1812 footprint dimension TG110-5050
Contextual Info: 80223 80223 10/100 MbpsTX/FX/10BT Ethernet Physical Layer Device PHY 98285 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

amp 269040-1

Abstract: 269040-1 MD400183
Contextual Info: 84225 84225 Quad 100BaseTX/FX/10BaseT Physical Layer Device 99061 PRELIMINARY This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

VALOR ST7033

Abstract: 8502e ST7033 "aui transformer" "aui transformers" 8501 xd 9346 EEPROM 8502a differential manchester encoder scematic symbols
Contextual Info: 8501/8502 Ethernet Mil to AUI Interface Adapter Technology, Incorporated PRELIMINARY DATA SHEET Features June 23, 1997 • Single Chip Connecting M il and A U I Interfaces Note: Check for latest Data Sheet revision before starting an y designs. ■ A U I Interface to Ethernet Transceiver

TQ80223

Contextual Info: smsc LAN83C183 PRELIMINARY STANDARD MICROSYSTEMS CORPORATION 10/100 Mbps TX/FX/10BT Ethernet Physical Layer Device PHY FEATURES Single Chip 100BASE-TX / FX/10BASE-T Physical Layer Solution Dual Speed -1 0 /1 0 0 Mbps Half And Full Duplex M il Interface To Ethernet Controller

Contextual Info: 84225 LSI LOGIC Quad 100BaseTX/FX/10BaseT Physical Layer Device PR ELIM INA R Y This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. 99061 Note: Check for latest Data Sheet revision before starting any designs.

Contextual Info: SEEQ Technology Incorporated 84220 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device Novem ber 19 1998 Note: Check for latest Data Sheet revision before starting any designs. Call SEEQ Technology 510 226-2903 — o r— SEEQ Data Sheets are n o w on the Web, access

Contextual Info: LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Product Features Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet Supports Burst Data Transfer 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers

L80225

Abstract: HALO TG22-3506ND TG22-3506ND LINK100 ssd schematic l80225/b LSI L80225
Contextual Info: L80225 10/100 MbpsTX/10BT Ethernet Physical Layer Device PHY Technical Manual Features • Single Chip 100Base-TX /10Base-T physical layer solution • On-chip wave shaping - no external filters required • Dual Speed - 10/100 Mbps • Baseline Wander Correction

Contextual Info: Advance Data Sheet August 1996 microelectronics group Lucent Technologies B e ll Labs In n o v a tio n s o DNCX06 Management Block ASIC Macrocell for 10/100Base-T PHYs Features Description • Interfaces directly to 10OTX, 10 0 T 4 ,10Base-T, and FX PMD macros

AUO 11101

Abstract: BEM 45
Contextual Info: 81400 Technology Incorporated Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support PRELIMINARY DATA SHEET March 8,1999 Features Note: Check for latest Data Sheet revision before starting any designs. Integrated Fast Ethernet controller and 10/100 megabit per second Mbps Physical Layer

Bt 2313

Abstract: L80227 L80C300 T601 transformerS BT 2313 M T591 BT 2313 M ic data
Contextual Info: TECHNICAL MANUAL L80227 10BASE-T/ 100BASE-TX Ethernet PHY October 2002 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

VALOR ST7033

Abstract: ST7033 "aui transformer" "aui transformers" "Attachment Unit Interface" lsi AUI lsi S553-1006 T55 transformer datasheet t90 series SCHEMATIC mda
Contextual Info: 8502 8502 Ethernet MII to AUI Interface Adapter 98210 Features Note: Check for latest Data Sheet revision before starting any designs. • Single Chip Connecting MII and AUI Interfaces SEEQ Data Sheets are now on the Web, at www.lsilogic.com. ■ AUI Interface to Ethernet Transceiver

Contextual Info: 84221 LSI LOGIC Quad 100BaseTX/10BaseT Physical Layer Device PR ELIM INA R Y This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. 99191 Note: Check for latest Data Sheet revision before starting any designs.

L84220

Abstract: HFBR-5103 ST6179 F840 L84225 LINK100 SOI RF transceiver IEEE 802.3 10BaseT L842 L84220 LSI
Contextual Info: L84225 100BaseTX/FX/10BaseT Physical Layer Device Technical Manual Features • Single-chip 100BaseTX/100BaseFX/ 10BaseT physical layer solution • Meets all applicable IEEE 802.3, 10BaseT, 100BaseTX and 100BaseFX standards • Four independent Channels in One IC

LAN91C111i-NE

Abstract: lan91c111-nu
Contextual Info: LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY PRODUCT FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ Datasheet Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet Supports Burst Data Transfer

8025g

Abstract: 10BT LINK100 TXCLK10
Contextual Info: 80220/80221 80220/80221 100BASE-TX/10BASE-T Ethernet Media Interface Adapter 98184 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs.

VALOR ST7033

Abstract: sT7033 8502 8502a plcc trasmitter "aui transformer" OUI15 CAP_TH 9346 EEPROM seeq EM2C
Contextual Info: 8502 8502 Ethernet MII to AUI Interface Adapter 98210 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

Contextual Info: LAN91C111 ADVANCED INFORMATION 10/100 Non-PCI Ethernet Single Chip MAC + PHY FEATURES ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet 8 Kbytes Internal Memory for Receive and

mjab

Contextual Info: LAN91C111 ADVANCED INFORMATION 10/100 Non-PCI Ethernet Single Chip MAC + PHY FEATURES § Single Chip Ethernet Controller § Dual Speed - 10/100 Mbps § Fully Supports Full Duplex Switched Ethernet § 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers

80225

Abstract: LSI 80225 NQ80225 NQ80220 BT 816
Contextual Info: 80225 80225 10/100 MbpsTX/10BT Ethernet Physical Layer Device PHY 99025 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

Contextual Info: L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.