NS 106 Search Results

Contextual Info: V73CAG01808RA HIGH PERFORMANCE 1Gbit DDR3 SDRAM 8 BANKS X 16Mbit X 8 - - - - I9 DDR3-1066 DDR3-1333 2.5 ns 2.5 ns Clock Cycle Time tCK7, CWL=6 1.875 ns 1.875 ns Clock Cycle Time ( tCK8, CWL=6 ) 1.875 ns 1.875 ns Clock Cycle Time ( tCK9, CWL=7 ) - 1.5 ns

24PIN

Abstract: CY7B193-12 CY7B193-15 CY7B193-20 CY7B197-12 CY7B197-15 CY7B197-20 EDI81256C-35 24PIN 1800 Hitachi Scans-001
Contextual Info: - 106 2 5 6 K m t, tt £ ïSKiÊSl CC X TAAC max ns) TCAC max (ns) CMOS 4 7 TOE max (ns) TOH (ns) / f TOD max (ns) S t a t i c RAM (2 6 2 14 4 x 1 ) 7' i l t t TWP min (ns) TDS min (ns) TDH min (ns) TWD min (ns) ma ÏÏI3X (ns i V D D or V C C (V) 2 4 P I N

Contextual Info: M O S E L V IT E L IC V53C16125H HIGH PERFORMANCE 128K X 16 B IT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE 40 PRELIMINARY 45 50 60 40 ns 45 ns 50 ns 60 ns 20 ns 22 ns 24 ns 30 ns Min. Fast Page Mode Cycle Time, tPC 23 ns 25 ns 28 ns 40 ns Min. Read/Write Cycle Time, (tRC)

Contextual Info: TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES - SODIMM _SMMS691A-AUGUST 1997 - REVISED NOVEMBER 1997 10 *CK3 10 ns *CK2 10 ns <AC3 7.5 ns *AC2 9 ns 12 12 ns 12 ns 8 ns 9.5 ns • • •

16v8

Abstract: 16v8 programming 16v8 spec palce16v8 programming guide PALCE16V8 PALCE16V8-10 PALCE16V8-15 PALCE16V8-25 PALCE16V8-5 PALCE16V8-7
Contextual Info: 16V8 PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL Device Features • Up to 16 input terms and 8 outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • 10 ns military/industrial versions 7 ns tCO 10 ns tS 10 ns tPD

Contextual Info: M O S E L V I TEL 1C V53C806H HIGH PERFORMANCE 1M x 8 B IT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE PRELIMINARY 40 45 50 60 Max. RAS Access Tim e, tRAC 40 ns 45 ns 50 ns 60 ns Max. Column Address Access Time, (tCAA) 20 ns 22 ns 24 ns 30 ns Min. Fast Page Mode Cycle Time, (tpc)

Contextual Info: M O S E L V /TE LiC V52C8128 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM 70 80 10 Max. RAS Access Time, tHAC HIGH PERFORMANCE V52C812B 70 ns 80 ns 100 ns Max. CAS Access Time, Ocac ) 20 ns 25 ns 25 ns Max. Column Address Access Time, (t*) 35 ns

12L10

Abstract: 16L6 20L10 20L8 PLDC20G10 PLDC20G10B ULTRA37000
Contextual Info: PLDC20G10B PLDC20G10 USE ULTRA37000 FOR ALL NEW DESIGNS CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns

20G10-25

Abstract: 20G10B-15 20G10B-20 Ultra37000TM 12L10 16L6 20L10 20L8 PLDC20G10 PLDC20G10B
Contextual Info: PLDC20G10B PLDC20G10 USE ULTRA37000 FOR ALL NEW DESIGNS CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns

TS27C256Q-25

Abstract: IMS27C256 TC57256D-25 TM57256AD-12 TM57256AD-120 TM57256AD-150 TM57H256D-70 TM57H256D-85 TMS27C256-1 TS27C256CQ-15
Contextual Info: - 10627C256 X -i -, m í± £ % TAAC max ns TCAC max (ns) —85 250 250 70 * ^ TOH max (ns) y f t tt A M h VIH min (V) tu ji/m î ï s V O H / 1 VOH min (V/mA) Co max (pF) (ns) TOD tax (ns) 100 90 4. 7 5 - 5 . 25 30/1 0.8 2.1) 6 1). 4/2.1 2. 4/0. 4 12 5

Contextual Info: M OSEL VI TEL IC V35644Q15KG 5.0 VOLT 4M x 64 HIGH PERFORMANCE UNBUFFERED DIMM MODULE HIGH PERFORMANCE 50 60 Max. RAS Access Tim e, tpj^c 50 ns 60 ns Max. CAS Access Tim e, (tcAc) 13 ns 15 ns Min. Cycle Time, (tpc) 84 ns 104 ns Min. EDO Mode Cycle Time, (tpc)

Contextual Info: PLDC20G10B/PLDC20G10 V CYPRESS Features • Fast — Commercial: tpjj = 15 ns, tc o = ns, t$ = 12 ns — Military: tpu = 20 ns, tç o = 15 ns, ts — 15 ns • Low power — I X max.: 70 mA, commercial — I c e max.: 100 mA, military • Commercial and military temperature

78F0948

Abstract: t p04 78009 NP-100 uPC393 IE-78K0-NS-A uPD780948 ID78K0-NS nec FPGA
Contextual Info: Preliminary User’s Manual IE-78K0-NS-P04 IE-780948-NS-EM4 Emulation Board and Probe Board for IE-78K0-NS-A Target device µPD780948 Subseries Document No. U14515EE1V0UM00 Date Published November 1999 NEC Corporation 1999 IE-78K0-NS-P04, IE-780948-NS-EM4

SN75112

Contextual Info: — 106- Dual Diff Line Driver 75112 T « H VlK áfe f* 1« MIN Ii = — 12mA A. - 9 tt * £ TYP M AX S - 0 .9 - 1 .5 V I.—»H 9 15 ns TI S N 75112 H—* L 9 15 ns FC 75112 L^H 16 25 ns NS MOT B 4 0 p F - -5 0 Q tpd m C, D H -» L Ic e " 13 25 ns 25 40

uPD780816

Abstract: 78009 uPC393 ID78K0-NS IE-78K0-NS-A
Contextual Info: Preliminary User’s Manual IE-78K0-NS-P04 IE-780818-NS-EM4 Emulation Board and Probe Board for IE-78K0-NS-A Target device µPD780816 A Subseries Document No. U14514EE2V0UM00 Date Published December 2000 NEC Corporation 2000 IE-78K0-NS-P04, IE-780818-NS-EM4

SN75112

Contextual Info: — 106- Dual D iff Line D r iv e r 75112 T « H VlK áfe f* 1« MIN Ii = — 12mA A. - 9 tt * £ TYP M AX S - 0 .9 - 1 .5 V I.—»H 9 15 ns TI S N 75112 H—* L 9 15 ns FC 75112 L^H 16 25 ns NS MOT B 4 0 p F - -5 0 Q tpd m C, D H -» L Ic e " 13 25 ns 25

SO-8 LTLS e3

Abstract: ltls e3 IC LTLS E3
Contextual Info: M O S E L V TTE U C PRELIMINARY V52C8256 MULTIPORT VIDEO RAM WITH 256K X 8 DRAM AND 5 1 2 X 8 SAM HIGH PERFORMANCE V52C8256 Max. RAS Access Tim e, tRAC 60 70 80 60 ns 70 ns 80 ns Max. CA S Access Time, (tcAc) 15 ns 20 ns 25 ns Max. Column Address Access Tim e, ( t ^ )

Contextual Info: 15$5. &! 15$5. &!$ 128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 12 ns • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data

78009

Abstract: uPC393 ID78K0-NS IE-78K0-NS-A
Contextual Info: Preliminary User’s Manual IE-78K0-NS-P04 IE-1615-NS-EM4 Emulation Board and Probe Board for IE-78K0-NS-A Target device µPD1615A Subseries Document No. U14617EE2V0UM00 Date Published January 2001 NEC Corporation 2001 IE-78K0-NS-P04, IE-1615-NS-EM4 This equipment complies with the EMC protection requirements.

SSR001

Contextual Info: IS61C632A IS61C632A 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM FEATURES • Fast access time: – 4 ns-125 MHZ; 5 ns-100 MHz; 6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and

palce16V8 programming

Abstract: palce16v8 programming guide palce16v
Contextual Info: PALCE16V8 Flash-Erasable Reprogrammable CMOS PAL Device Features • Up to 16 input terms and eight outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • Active pull-up on data input pins • Low power version 16V8L — 55 mA max. commercial (10, 15, 25 ns)

Contextual Info: M O S E L V I T E L 1C V35642R05KG 5.0 VO LT2 M x 64 H IG H PER FO R M A NC E U NBUFFERED D IM M EDO M O D U LE HIGH PERFORMANCE 50 60 Max. RAS Access Tim e, tpj^c 50 ns 60 ns Max. CAS Access Tim e, (tcAc) 13 ns 15 ns Min. Cycle Time, (tpc) 84 ns 104 ns

Contextual Info: M O S E L V I T E L 1C V33642R05KG 3.3 VO LT2 M x 64 H IG H PER FO R M A NC E U NBUFFERED D IM M EDO M O D U LE HIGH PERFORMANCE 50 60 Max. RAS Access Time, tRAc 50 ns 60 ns Max. CAS Access Time, (tcAc) 13 ns 15 ns Min. Cycle Time, (tpc) 84 ns 104 ns Min. EDO Mode Cycle Tim e, (tpc)

RAS 05

Contextual Info: M O S E L V I T E L 1C V33644Q15KG 3.3 V O L T 4 M x 64 H IG H P ER FO R M A NC E U NBUFFERED D IM M M O D U LE HIGH PERFORMANCE 50 60 Max. RAS Access Time, tRAc 50 ns 60 ns Max. CAS Access Time, (tcAc) 13 ns 15 ns Min. Cycle Time, (tpc) 84 ns 104 ns Min. EDO Mode Cycle Time, (tpc)