NON-BLOCKING STS-1 SWITCHING ARCHITECTURE Search Results

8b/10b encoder

Abstract: serdes 8b 10b PM5310 PM5372 PM7390 STS-192 STS-48 Optical Receiver LVDS
Contextual Info: PMC-Sierra,Inc. PM5372 TSE Preliminary 40 Gbit/s Transport Switching Element FEATURES • Implements a Time-Space-Time fabric with STS-1/AU-3 granularity. • Provides 64 ingress STS-12 equivalent ports for a total of 64*12 = 768 STS-1 flows. • Supports non-blocking permutation

PM5310

Abstract: PM5372 PM7390 STS-192 STS-48
Contextual Info: PMC-Sierra,Inc. PM5372 TSE Preliminary 40 Gbit/s Transport Switching Element FEATURES • Implements a Time-Space-Time fabric with STS-1/AU-3 granularity. • Provides 64 ingress STS-12 equivalent ports for a total of 64*12 = 768 STS-1 flows. • Supports non-blocking permutation

VSS011

Abstract: TA-NWT-000253 r7t marking code 000241 16T MARKING PM5361 PM5371 TU12 10D41
Contextual Info: PMC S TANDARD PRODUCT PMC-Sierra, Inc. PM5371 TUDX SONET/SDH TRIBUTARY UNIT CROSS CONNECT FEA TU R ES • A single stage, non-blocking array of time switches for cross-connecting SONET virtual tributaries VTs or SDH tributary units (TUs). • Provides non-blocking switching between two STS-3 (STM-1) byte serial input

Contextual Info: PMC-Sierra, Inc. S TANDARD PRODUCT PM5371 TUDX SONET/SDH TRIBUTARY UNIT CROSS CONNECT FEA TU R ES • A single stage, non-blocking array of time switches for cross-connecting SONET virtual tributaries VTs or SDH tributary units (TUs). • Provides non-blocking switching between two STS-3 (STM-1) byte serial input

Contextual Info: PM5337 ADM 622 Preliminary 56 1: 02 :3 LOW / HIGH ORDER CROSSCONNECT r, 20 04 • Integrated 2.5Gbit/s non-blocking memory based cross-connect supporting anycast traffic • Support switching at STS/AU/VT/TU level and all legal concatenations • Integrated MAPS processing for

Contextual Info: TM VTXP-24 Device 1.25 Gbps Virtual Tributary Processor with Integrated Scalable VT/STS & VC/AU3 Switch TXC-06970 PRODUCT INFORMATION FEATURES • Line or Client interfaces - Dual CML 2.488 Gbit/s TFI-5 compliant shared with terminal and interconnect interfaces

SPRU007

Abstract: BIOS example delay source code BIOS example source code cdb 442 Device Name 23 330 mbx 202 C5000 SPRU103 TMS320 TMS320C5000
Contextual Info: TMS320C5000 DSP/BIOS Application Programming Interface API Reference Guide Literature Number: SPRU404F May 2003 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services

tlu 011

Abstract: CP12 CP14 CP15 CRC-32 32 bit SECDED* encoder adds 5 bit ecc optical fiber free book smart card K001 "routing tables"
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. C-5 Network Processor Architecture Guide C-5 NP D0 Release For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. C-Port Corporation

Contextual Info: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC NOVEMBER 2007 REV. P1.0.2 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/

traffic light using 68K

Abstract: MCP860 AU-AIS alarm
Contextual Info: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC SEPTEMBER 2007 REV. P1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/

G706

Abstract: truth table varification
Contextual Info: XRT86SH328 PRELIMINARY SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC SEPTEMBER 2007 REV. P1.0.1 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/

XRT91L31

Contextual Info: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC JUNE 2010 REV. 2.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to

user manual of XRT91L31

Contextual Info: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to

T85 Slide Switch

Abstract: HP SLM MCP860 vt6 transistor 49Mhz power amplifier AU-AIS i860 64-Bit Microprocessor Performance Brief LTE DL Channel Encoder transformer e19 working of 5 pin relay t73
Contextual Info: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC AUGUST 2008 REV. 1.0.1 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/

SPRH097

Abstract: C5000 C6000 SPRU103 TMS320 TMS320C5000 SPRU103E sem 2106 manual sem 2106 schematic code composer studio 3.3 programs
Contextual Info: TMS320C5000 DSP/BIOS Application Programming Interface API Reference Guide Literature Number: SPRU404D November 2001 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,

engine control module seg np2

Abstract: tlu 115 tlu 011 CP15 CRC-32 CP12 CP14 l 83s 472 722 C3E 351 IBM powerpc 405 GPr 266MHz PROCESSOR
Contextual Info: Architecture Guide C-5e/C-3e NETWORK PROCESSOR SILICON REVISION B0 C5EC3EARCH-RM Rev 04 PRODUCTION Freescale Semiconductor, Inc., 2004. All rights reserved. Architecture Guide C-5e/C-3e Network Processor Silicon Revision B0 C5EC3EARCH-RM Rev 04 How to Reach Us:

MT28F128J3

Abstract: MT28F320J3 MT28F640J3 64-BALL
Contextual Info: 128Mb, 64Mb, 32Mb Q-FLASH MEMORY MT28F128J3, MT28F640J3, MT28F320J3 Q-FLASH MEMORY Features Figure 1: 56-Pin TSOP Type I Memory Organization • x8/x16 • One hundred twenty-eight 128KB erase blocks 128Mb • Sixty-four 128KB erase blocks (64Mb) • Thirty-two 128KB erase blocks (32Mb)

sem 2106 manual

Abstract: free sem 2106 28 DSP/BIOS mbx 202 mbx 202 schematic dpi 282 BIOS example source code SPRU625A Device Name 23 330 C2000
Contextual Info: TMS320C28x DSP/BIOS Application Programming Interface API Reference Guide Literature Number: SPRU625A April 2003 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services

M904

Contextual Info: 256Mb, 128Mb, 64Mb, 32Mb Q-FLASH MEMORY  MT28F256J3‡, MT28F128J3, MT28F640J3, MT28F320J3 Q-FLASH MEMORY Features Figure 1: 56-Pin TSOP Type I Memory Organization • x8/x16 • Two hundred fifty-six 128KB erase blocks 256Mb • One hundred twenty-eight 128KB erase blocks

Contextual Info: 256Mb, 128Mb, 64Mb, 32Mb Q-FLASH MEMORY  MT28F256J3‡, MT28F128J3, MT28F640J3, MT28F320J3 Q-FLASH MEMORY Features Figure 1: 56-Pin TSOP Type I Memory Organization • x8/x16 • Two hundred fifty-six 128KB erase blocks 256Mb • One hundred twenty-eight 128KB erase blocks

12 pin 7 segment display layout -LD-5461BS

Abstract: sample code read and write flash memory 4 digit 7 segment display pin configuration 4 digit 7 segment display 18 pin configuration dual digit 7 segment display 18 pin 2 digit 7 segment display 8 pin configuration 2 digit 7 segment display pin configuration dual 7 segment display pin configuration block diagram of diode operation Micron data sheet Q-Flash
Contextual Info: 256Mb, 128Mb, 64Mb, 32Mb Q-FLASH MEMORY  MT28F256J3‡, MT28F128J3, MT28F640J3, MT28F320J3 Q-FLASH MEMORY Features Figure 1: 56-Pin TSOP Type I Memory Organization • x8/x16 • Two hundred fifty-six 128KB erase blocks 256Mb • One hundred twenty-eight 128KB erase blocks

VT138

Abstract: ASA17
Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH SEPTEMBER 2006 REV. P1.0.1 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

Contextual Info: ATtiny87/ATtiny167 8-bit AVR Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller DATASHEET Features ● High performance, low power Atmel AVR 8-bit microcontroller ● Advanced RISC architecture ● 123 powerful instructions – most single clock cycle execution

EM6819

Abstract: EM MICROELECTRONIC-MARIN EM6819 CR816L PB-DIN2 CoolRISC 816L PA6.6 em6819 nvm write
Contextual Info: R EM MICROELECTRONIC - MARIN SA EM6819 Sub-1V 8bit Flash MCU DC-DC Converter, E2PROM Architecture Description The EM6819 is designed to be battery operated for extended lifetime applications. Its large voltage range from 3.6V down to 0.9V makes it a perfect match for today’s