NLG72 Search Results

Contextual Info: IDT - Integrated Device Technology Page 1 of 2 Integrated Device Technology Products | Applications Clock / Timing Devices | Search PC Motherboard Clocks 9LPRS397EKLFT | Support The Analog and Digital Company | Investor | About IDT Mobile > 9LPRS397 > 9LPRS397EKLFT

NLG72

Abstract: gps 1pps holdover GR-253-CORE
Contextual Info: Dual Synchronous Ethernet Line Card PLL FEATURES • HIGHLIGHTS • Dual PLL chip: • Provides clocks for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements • Provides clocks for Cellular and WLL base-station (GSM and 3G

history of automatic phase selector

Abstract: IDT82V3399 NLG72 82V3399B gps 1pps holdover 1pps IEEE1588 NLG7282V3399B
Contextual Info: SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588 FEATURES • HIGHLIGHTS • Single chip PLL: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64)

Contextual Info: SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588 • FEAT U RES HIGHLIGHTS • Single chip PLL: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64)

Contextual Info: Dual Synchronous Ethernet Line Card PLL FEATURES • • HIGHLIGHTS • Dual PLL chip: • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements • Provides node clocks for Cellular and WLL base-station (GSM

CK410

Abstract: NLG72 VFQFPN DB1900GS
Contextual Info: Search Entire Site Contact IDT | Investors | Press Document Search | Package Search | Parametric Search | Cross Reference Search | Green & RoHS | Calculators | Thermal Data | Reliability & Quality | Military Home > Products > Clock / Timing Devices > PC-Notebook-Server Clocks > PCIe/HCSL Buffers and Generators > 9FG1900-1 >

Contextual Info: Dual Synchronous Ethernet Line Card PLL • FEAT U RES HIGHLIGHTS • Dual PLL chip: • Provides clocks for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements • Provides clocks for Cellular and WLL base-station (GSM and 3G

tms 1944

Abstract: 741 Ic1
Contextual Info: SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588 FEATURES • HIGHLIGHTS • Single PLL chip: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet SyncE • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64)