NCC JAA Search Results

Contextual Info: 2 MEG x 8 EDO DRAM M IC R O N HRAM MT4LC2M8E7 MT4C2M8E7 U n M IV I FEATURES PIN ASSIGNMENT (Top View OPTIONS 28-Pin SOJ (DA-3) Vcc [ 1* DÛ1 [ 2. DQ2¿ 3 003 r 4 DQ4 5 WE# C 6 RAS# C 7 NCC 3 AIO L 9 A0 L 10 A1 C t t A2 12 A3 t 13 Vcc [ 14 MARKING • Voltages

25C256KI-1

Abstract: 25C256KI 25C128 25C256 CAT25C128 CAT25C256
Contextual Info: Advanced Information CAT25C128/256 128K/256K-Bit SPI Serial CMOS E2PROM FEATURES • 100,000 Program/Erase Cycles ■ 5 MHz SPI Compatible ■ 100 Year Data Retention ■ 1.8 to 6.0 Volt Operation ■ Self-Timed Write Cycle ■ Hardware and Software Protection

w02 marking

Abstract: Matsuo 501 T02 6A NCC JAA "package marking code" 162 matsuo jaa
Contextual Info: MINIATURE MOLDED CIRCUIT PROTECTOR TYPE CAUTIONS JAA • Please confirm the condition of use and product specifications. • Please should not exceed the rated voltage. • This catalog is designed for providing general information. Please inquire of our Sales Department to confirm specifications prior

486 SX

Abstract: 272769
Contextual Info: * EMBEDDED lntel486TM SX PROCESSOR • 32-Bit RISC Technology Core ■ Boundary Scan JTAG ■ 8-Kbyte Write-Through Cache ■ 3.3-Volt Processor — 208-Lead Shrink Quad Flat Pack (SQFP) ■ Four Internal Write Buffers ■ Burst Bus Cycles ■ Dynamic Bus Sizing for 8- and 16-bit

29021

Contextual Info: 82505TA MULTIPORT REPEATER CONTROLLER MPR • Complies with IEEE 802.3 CSMA/CD Standard for Repeaters (Std ANSI/IEEE 802.3c-1988) ■ _ Jam Signal Generation ■ 10-Mb/s Operation " Eight-Bit Blinding Timer at End of Transmission ■ Allows Up to Eleven Twisted Pair Ports

Contextual Info: Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation - Single Cycle Reprogram Erase and Program - 2048 Pages (264 Bytes/Page) Main Memory • Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of

74L154

Abstract: twido 290213 10BASE2 10BASE5 82504TA 82505TA T7200
Contextual Info: in te i 82505TA MULTIPORT REPEATER CONTROLLER MPR Complies with IEEE 802.3 CSMA/CD Standard for Repeaters (Std ANSI/IEEE 8 02 .3c -1988) Jam Signal Generation 10-Mb/s Operation Eight-Bit Blinding Timer at End of Transmission Pin-Selectable FIFO Fill Level

Contextual Info: H A R R DG506A/DG507A IS S E M I C O N D U C T O R 16-Channel/Dual 8-Channel CMOS Analog Multiplexer GENERAL DESCRIPTION. FEATURES The DG506A/DG507A are CMOS monolithic 16-channel and dual 8-channel analog multiplexers, which can also be used as demultiplexers. The DG506A uses 4 address inputs

Contextual Info: Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation - Single Cycle Reprogram Erase and Program -1 0 2 4 Pages (264 Bytes/Page) Main Memory • Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of

17-33

Abstract: CAT25C03 0003FF
Contextual Info: Advanced CAT25C03/05/09/17/33 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM FEATURES 1,000,000 Program/Erase Cycles • 10 MHz SPI Compatible 100 Year Data Retention ■ 1.8 to 6.0 Volt Operation Self-Timed Write Cycle ■ Hardware and Software Protection 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP

Contextual Info: IfiK PRELIMINARY INFORMATION AU Commercial Industrial X24LC04 X24LC04I r 10vBBi » bi i d h x Electrically Erasable PROM TYPICAL FEATURES • 3 V -6 V Vcc Operation • Low Power CMOS — 2 mA Active Current Typical —60 jliA Standby Current Typical • Internally Organized as Two Pages

X2404 P

Abstract: x2404
Contextual Info: J Atl 4K ü a r Commercial X2404 m o v a oit Industrial_X2404I_ 5 1 2 x 8 Bl t Electrically Erasable PROM TYPICAL FEATURES • Internally Organized as Two Pages — Each 256 x 8 • 2 Wire Serial Interface • Provides Bidirectional Data Transfer

Contextual Info: in ttJ o ^ iy i» w 8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER • 25 MHz Operation at 4.5-5.5 Volts ■ 1 Mbyte of Linear Address Space ■ Optional 4 Kbytes of ROM ■ 1000 Bytes of Register RAM ■ Register-register Architecture ■ 32 I/O Port Pins

Contextual Info: Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation -S in g le Cycle Reprogram Erase and Program - 4096 Pages (264 Bytes/Page) Main Memory • Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of

PST34

Contextual Info: H YU N D AI H Y 5 1 1 6 1 6 4 B S e r ie s 1M X 16-bit CMOS DRAM with Extended Data Out DESCRIPTION The HY5116164B is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY5116164B utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide

Contextual Info: Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation - Single Cycle Reprogram Erase and Program - 2048 Pages (264 Bytes/Page) Main Memory • Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of

CAT25C03

Contextual Info: Advanced Information CAT25C03/05/09/17 2K/4K/8K/16K SPI Serial CMOS E2PROM FEATURES 1,000,000 Program/Erase Cycles • 10 MHz SPI Compatible 100 Year Data Retention ■ 1.8 to 6.0 Volt Operation Self-Timed Write Cycle ■ Hardware and Software Protection 8-Pin DIP/SOIC and 14-Pin TSSOP

CAT25C02

Abstract: 25c02
Contextual Info: Advanced CAT25C02/04/08/16/32 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM FEATURES 1,000,000 Program/Erase Cycles • 10 MHz SPI Compatible 100 Year Data Retention ■ 1.8 to 6.0 Volt Operation Self-Timed Write Cycle ■ Hardware and Software Protection 8-Pin DIP/SOIC, 16-Pin SOIC, 8-Pin TSSOP and

INTEL I7 microprocessor circuit diagram

Abstract: applications of 8085 microprocessor in mobile phones Mitel Integrated DTMF 8085 microprocessor pin description 8085 intel microprocessor block diagram DTMF mobile MT8870 dtmf decoder pin description of mt8870 20MS MT8870
Contextual Info: MT8885 MITEL Integrated DTM F Transceiver with Preliminary Information Power Down and A d ap tive M icro Interface ISSUE 2 Features O rdering Inform ation C entral office quality DTMF tran sm itter/receiver • S ingle 5 Volt pow er supply • A daptive m icro interface enables com patibility

4218160

Abstract: NEC 4218160 nec A2C UPD42S18160
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /JPD42S18160,4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The /tPD42S18160, 4218160 are 1,048,576 words by 16 bits CMOS dynamic RAMs. The fast page mode and byte read/write mode capability realize high speed access and low power consumption.

Contextual Info: HN62W428 Series 8M 512K x 16-bit and (1M x 8-bit) Mask ROM • DESCRIPTION The Hitachi HN62W 428 Series is an 8-M egabit CMOS Mask Program mable Read Only M em ory organized either as 524,288 x 16-bit or as 1,048,576 x 8-bit. The low voltage and low power consumption of this device

Contextual Info: intei 5164 HIGH SPEED 8192 x 8-BIT STATIC RAM 5164-20 5164-25 5164-30 5164-35 Max Access Time ns 20 25 30 35 Max Active Current (mA) 120 110 100 100 Max Standby Current (mA) 30 30 30 30 Static Operation — No Clock/Refresh Required • Power Down Mode Equal Access and Cycle Times

Contextual Info: ¡n tg l M5164/M5164L HIGH-SPEED 8,192 x 8 BIT CMOS STATIC RAM Standard M ilitary Drawings # 5962-89691 & # 5962-85525 -25 -35 -45 -70 Max. Access Time ns 25 35 45 70 Max. D.C. Supply Current (mA) 110 100 100 100 Max. Standby Current (mA) 20 20 20 20 High-Speed Address/Chip Select

ma710pc

Abstract: a710 MA710 UA710C Fairchild uA710 MA710C 710c a710c UA710
Contextual Info: HÄ710 HIGH SPEED DIFFERENTIAL COMPARATOR F A IR C H IL D L IN E A R INTEGRATED CIRCUIT G E N E R A L D E S C R I P T I O N — T h e m A 7 1 0 is a D iffe re n tia l V o lta g e C o m p a ra to r in te n d e d fo r a p p lica tio n s re q u irin g hig h a ccu ra cy and fast response tim es. It is c o n stru cte d on a sin gle s ilic o n c h ip