NB100LVEP Search Results

N100

Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

LVEP221

Abstract: NB100LVEP221 NB100LVEP221FA NB100LVEP221FAR2
Contextual Info: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential

Contextual Info: NB100LVEP17 2.5V / 3.3V Quad Differential Driver/Receiver Description The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

Contextual Info: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver Description The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential

N100

Abstract: NB100LVEP91 NB100LVEP91DW NB100LVEP91DWR2 qfn-24 4x4
Contextual Info: NB100LVEP91 2.5V / 3.3V Any Level Positive Input to −2.5V / −3.3V / −5V NECL Output Translator The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

LQFP-64

Abstract: LVEP224 NB100LVEP224 NB100LVEP224FA NB100LVEP224FAR2
Contextual Info: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low

Contextual Info: NB100LVEP91 2.5V / 3.3V Any Level Positive Input to −2.5V / −3.3V / −5V NECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

100LVEp

Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V/−5 V NECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

LQFP-64 thermal pad

Contextual Info: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1−to−24 differential clock driver, designed with clock distribution in mind, accepting two clock

transistor N100 pinout

Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

Contextual Info: NB100LVEP56 2.5V / 3.3V / 5V ECL Dual Differential 2:1 Multiplexer The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both

N100

Abstract: NB100LVEP91
Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

N100

Abstract: NB100LVEP56 NB100LVEP56DT NB100LVEP56DTR2 NB100LVEP56MN TSSOP-20 LVEP
Contextual Info: NB100LVEP56 2.5V / 3.3V / 5V ECL Dual Differential 2:1 Multiplexer The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both

QFN 64 8x8 footprint

Abstract: QFN-52 LVEP222 MC100LVE222 NB100LVEP222
Contextual Info: NB100LVEP222 2.5 V/3.3 V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential

Contextual Info: NB100LVEP222 2.5V/3.3V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single-ended with VBB output reference bypassed and connected to

Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver Description The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

Contextual Info: NB100LVEP56 2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer Description The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both

N100

Abstract: NB100LVEP91 NB100LVEP91DW NB100LVEP91DWR2 D 1875 d1875
Contextual Info: NB100LVEP91 Product Preview 2.5V / 3.3V Any Level Input to −2.5V / −3.3V / −5V NECL Output Translator The NB100LVEP91 is a triple any level input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential -2.5 V / -3.3

Contextual Info: NB100LVEP224 Product Preview 2.5V/3.3VĄ1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable The NB100LVEP224 is a low skew 1–to–24 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low

LVEP222

Abstract: MC100LVE222 NB100LVEP222 NB100LVEP222FA
Contextual Info: NB100LVEP222 2.5V/3.3V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended with VBB output reference bypassed

100LVEP

Abstract: LVEP221
Contextual Info: NB100LVEP221 Product Preview 2.5V/3.3VĄ1:20 Differential HSTL/ECL/PECL Clock Driver The NB100LVEP221 is a low skew 1–to–20 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential

LVEP221

Abstract: MC100EP221 NB100LVEP221 LQFP "100 pin" PACKAGE
Contextual Info: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver Description The NB100LVEP221 is a low skew 1−to−20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential