NAND GATE LAYOUT Search Results

ic cmos 4014

Abstract: 408000 144 p LQFP PACKAGE
Contextual Info: Sea-of-Gate Type CMOS Gate Arrays CG51 Series Features High integration: Maximum 753,768 BCs on chip Technology: Silicon-gate, 3-layer metal wiring Base circuit (basic cell): 2-input NAND/2-input NOR gates Gate delay time: 210 ps (High-speed type 2-input NAND f/o=2 standard load)

Contextual Info: OBSOLETE 100304 www.ti.com SNOS120B – AUGUST 1998 – REVISED APRIL 2013 100304 Low Power Quint AND/NAND Gate Check for Samples: 100304 FEATURES DESCRIPTION • • • • The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-NOR of all five AND gate

D4011

Abstract: 4011U
Contextual Info: ¡3 HARRIS C D 4 0 1 1 U B T yp e s CMOS Quad 2-Input NAND Gate High-Voltage Types 20-Volt Rating m CD4011UBquad 2-input NAND gate provides the system designer with direct implementation o f the NAND func­ tion and supplements the existing fam ily of CMOS gates.

Contextual Info: ^ Tex a s In s t r u m e n t s CD4011UB Types Data sheet acquired from Harris S em iconductor S C H S 022 CMOS Quad 2-Input NAND Gate High-Voltage Types 20-Volt Rating • CD4011UB quad 2-input NAND gate provides the system designer with direct Implementation of the NAND func­

JESD30E

Abstract: 74AUP1G00
Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a

Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a

HEF4093BP

Abstract: hef4093 HEF4093BT HEF4093BP applications HEF4093B HEF4093BPN HEF4093BD MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN logic gates circuit diagram HEF4093BTD
Contextual Info: HEF4093B gates J QUADRUPLE 2-INPUT NAND SCHMITT TRIGGER The HEF4093B consists o f four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive and

Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a

Contextual Info: Macro-Embedded Type Celt Arrays • CE46 Series Features High integration: Technology: Gate delay time: Maximum 198,084 BCs on chip Si-gate CMOS, 2-layer metal Standard gate tpd=360 ps (2-input NAND, standard load, V dd=5 V) tpd=520 ps (2-input NAND, standard load, V dd=3.3 V)

NAND 74 SOT353

Abstract: 74LVC1G00 A115-A
Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74LVC1G00 is a single 2-input positive NAND gate with Top View a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The

A115-A

Abstract: DFN1410 ds3221
Contextual Info: 74LVCE1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVCE1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.4V to 5.5V. A 1

74AHCT1G00

Abstract: A115-A VM MARKING CODE SOT353
Contextual Info: 74AHCT1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74AHCT1G00 is a single 2-input positive NAND gate Top View with a standard totem pole output. The device is designed for operation with a power supply range of 4.5V to 5.5V. The

74LVC1G00

Abstract: A115-A DFN1410 Single 2-Input AND GATE type name
Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The

toshiba smd marking code transistor

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview MC74LCX38 Low-Voltage CMOS Quad 2-Input NAND Gate, Open Drain With 5V-Tolerant Inputs The MC74LCX38 is a high performance, open drain quad 2–input NAND gate operating from a 2.7 to 3.6V supply. High impedance TTL

Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The

Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard push-pull output. The device is designed for A 1 operation with a power supply range of 1.65V to 5.5V. The

Contextual Info: 74AHC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Pin Assignments Description The 74AHC1G00 is a single 2-input positive NAND gate with Top View a standard push-pull output. The device is designed for operation with a power supply range of 2.0 V to 5.5 V. The

74AHC1G00

Abstract: A115-A 74AHC1G00SE-7
Contextual Info: 74AHC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74AHC1G00 is a single 2-input positive NAND gate with Top View a standard push-pull output. The device is designed for operation with a power supply range of 2.0 V to 5.5 V. The

SOT35

Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard push-pull output. The device is designed for A 1 5 operation with a power supply range of 1.65V to 5.5V. The

Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74LVC1G00 is a single 2-input positive NAND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to

Contextual Info: 74LVCE1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74LVCE1G00 is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.4V to 5.5V. A 1 B 2 5 Vcc

Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed ( Top View ) for low power and extended battery life in portable applications. ( Top View ) A 1 The 74AUP1G00 is a single 2-input positive NAND gate with a

Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View ( Top View ) The 74LVC1G00 is a single 2-input positive NAND gate with A 1 a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The

hef4093b

Abstract: schmitt trigger application sheet HEF4093BC HEF4093BP
Contextual Info: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 8 — 21 November 2011 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The