MUX65 Search Results

C127

Abstract: STE2001 STE2002 STE2002DIE1 STE2002DIE2 TC4-14 -TR mux 8-1 mux 8*1 48nd MUX65
Contextual Info: STE2002 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 104 x 128 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling

STE2004DIE1

Abstract: c5966 C8188 D4185 C101 STE2001 STE2002 STE2004 STE2004DIE2 C4754
Contextual Info: STE2004 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling

ic HS 2272

Abstract: C8188 HS 2272 C101 STE2004S D4185
Contextual Info: STE2004S 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES ■ 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode

lcd cog spi 96x49

Abstract: STE2007 96x49 PAD85 COM19 LR019 lcd cog 51435
Contextual Info: STE2007 96 x 68 Single Chip LCD Controller/Driver Features • 68 x 96 bits Display Data RAM ■ 33,49, 65 and 68 Lines Mode ■ Row by Row Scrolling ■ Interfaces – 3-lines Serial Interface read and write – I2C (read and write) – 4-Line Serial (read and write)

st DB3 c126

Abstract: C127 MUX81 STE2001 STE2002 DB3 C109 D0227
Contextual Info: STE2002 81 x 128 single-chip LCD controller/driver Features – Eight selectable temperature compensation coefficients • 104 x 128 bits Display Data RAM ■ Programmable MUX rate ■ Programmable frame rate ■ ■ Designed for chip-on-glass COG applications

NF 841

Abstract: 2905 transistor datasheet 4221 transistor datasheet 64 x 102 pixels matrix LCD controller/driver COL83 3307 MOS 3843 application note ic 841 t4 3570 datasheet COL101
Contextual Info: INTEGRATED CIRCUITS DATA SHEET PCF8812 65 x 102 pixels matrix LCD driver Product specification Supersedes data of 2000 Nov 22 2004 Feb 23 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 CONTENTS 1 FEATURES 2 APPLICATIONS

ic HS 2272

Abstract: high voltage booster 96x68 STE2007 96x49 g s technology STE2007DIE2 96X65
Contextual Info: STE2007 96 x 68 Single Chip LCD Controller/Driver Features • 68 x 96 bits Display Data RAM ■ 33,49, 65 and 68 Lines Mode ■ Row by Row Scrolling ■ Interfaces – 3-lines Serial Interface read and write – I2C (read and write) – 4-Line Serial (read and write)

ST T4 3570

Abstract: 3885 7811 Philips pixels matrix LCD controller driver 9346 PC8812-1
Contextual Info: INTEGRATED CIRCUITS DATA SHEET PCF8812 65 x 102 pixels matrix LCD driver Product specification File under Integrated Circuits, IC12 2000 Nov 22 Philips Semiconductors Product specification 65 × 102 pixels matrix LCD driver PCF8812 CONTENTS 10 INSTRUCTIONS

MUX 8-1

Abstract: 48nd MUX81 tr 9465
Contextual Info: STE2002 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES ■ 104 x 128 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling

Contextual Info: STE2004 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling

db3 c53

Abstract: transistor code R74 transistor M 839 STE2002 code mx stmicroelectronics db3 c103 nv ram data sheet MUX 8-1 C127 MUX81
Contextual Info: STE2002 81 x 128 single-chip LCD controller/driver Features – Eight selectable temperature compensation coefficients • 104 x 128 bits Display Data RAM ■ Programmable MUX rate ■ Programmable frame rate ■ ■ Designed for chip-on-glass COG applications

R6217

Abstract: 102X8 l97c
Contextual Info: STE2004 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling

Contextual Info: STE2004 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES ■ 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode

PDC20

Abstract: C101 STE2004 STE2004DIE1 STE2004DIE2 D4185 R51 13H
Contextual Info: STE2004 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER 1 • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES ■ 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode

R51 13H

Abstract: ic HS 2272 C101 STE2004S 52c45 LR0050 C8391 lr0114 102X8 lcd cog spi
Contextual Info: STE2004S 102 x 65 single-chip LCD controller/driver Features Description • 102 x 65 bits display data RAM ■ Programmable MUX rate ■ Programmable frame rate ■ X,Y programmable carriage return ■ Dual partial display mode ■ Row by row scrolling The STE2004S is a low power CMOS LCD

cs960

Abstract: 9225y FR-1 lr0114 R51 13H
Contextual Info: STE2004S 102 X 65 single chip LCD controller / driverr Features Description • 102 x 65 bits display data RAM ■ Programmable MUX rate ■ Programmable frame rate ■ X,Y programmable carriage return ■ Dual partial display mode ■ Row by row scrolling

ic HS 2272

Abstract: power supply ic 1507 STE2007 96x49 lcd cog spi 96x49
Contextual Info: STE2007 96 x 68 Single-chip LCD controller/driver Features • 68 x 96 bits Display Data RAM ■ 33,49, 65 and 68 Lines mode ■ Row by row scrolling ■ Interfaces – 3-lines Serial Interface read and write – I2C (read and write) – 4-Line serial (read and write)

LR0050

Abstract: 3086 p electronic series and parallel circuits flowing r51 c/1 tc 3086 C101 STE2004 STE2004DIE1 STE2004DIE2 LR0111
Contextual Info: STE2004 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER 1 FEATURES • 102 x 65 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling N-Line Inversion Automatic data RAM Blanking procedure