MUX10 Search Results

mux 18

Abstract: DWDm MUX100G-X Nanovation Technologies
Contextual Info: MUX100G-X 100GHz DWDM MUX/DMUX Features • Low Insertion Loss • High Isolation • High Wavelength Stability • High Reliability Full Metalized Package Specifications Number of Channels 8 16 Center Wavelength (nm) 1548.51 ~ 1560.61 (ITU-T Grid) Channel Bandwidth (nm)

71M6543GT/71M6543GHT

Contextual Info: EVALUATION KIT AVAILABLE 71M6543FT/71M6543HT/ 71M6543GT/71M6543GHT General Description The 71M6543FT/71M6543HT/71M6543GT/71M6543GHT 71M654xT are 4th-generation three-phase metering systems-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power RTC with digital temperature

Contextual Info: EVALUATION KIT AVAILABLE 71M6545T/71M6545HT General Description The 71M6545T/71M6545HT metrology processors are based on Maxim Integrated’s 4th-generation metering architecture supporting the 71M6xxx series of isolated current sensing products that offer drastic reduction in

Contextual Info: ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561 – JUNE 2012 Analog Front-End for Power Monitoring, Control, and Protection Check for Samples: ADS131E04, ADS131E06 , ADS131E08 FEATURES 1 • • 23 • • • • • • • • Eight Differential Current and Voltage Inputs

Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685A − DECEMBER 2002 − REVISED FEBRUARY 2003 D High Performance 1:5 PLL Clock D D D D D D D D D D D D D D D Synchronizer Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock

LF43168

Abstract: lifo 001H HSP43168 8 tap fir filter MUX10
Contextual Info: LF43168 LF43168 DEVICES INCORPORATED Dual 8-Tap FIR Filter Dual 8-Tap FIR Filter DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 66 MHz Data and Computation Rate ❑ Two Independent 8-Tap or Single 16-Tap FIR Filters ❑ ❑ ❑ ❑ 10-bit Data and Coefficient Inputs

Contextual Info: HSP43168 Data Sheet July 27, 2009 FN2808.12 Dual FIR Filter Features The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a

MUX21

Abstract: CDC7005 MUX22
Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685E − DECEMBER 2002 − REVISED NOVEMBER 2004 D High Performance 1:5 PLL Clock D D D D D D D D D D D D D D D Synchronizer Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock

Contextual Info: EVALUATION KIT AVAILABLE 71M6545T/71M6545HT General Description The 71M6545T/71M6545HT metrology processors are based on Maxim Integrated’s 4th-generation metering architecture supporting the 71M6xxx series of isolated current sensing products that offer drastic reduction in

71M6542GT-IGT/F

Contextual Info: EVALUATION KIT AVAILABLE 71M6541DT/71M6541FT/71M6541GT/ 71M6542FT/71M6542GT General Description The 71M6541DT/71M6541FT/71M6541GT/71M6542FT/ 71M6542GT 71M654xT are 4th-generation singlephase metering systems-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power RTC with digital

Contextual Info: EVALUATION KIT AVAILABLE 71M6545T/71M6545HT General Description The 71M6545T/71M6545HT metrology processors are based on Maxim Integrated’s 4th-generation metering architecture supporting the 71M6xxx series of isolated current sensing products that offer drastic reduction in

Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685I − DECEMBER 2002 − REVISED APRIL 2006 D High Performance 1:5 PLL Clock D D D CTRL_ CLK CTRL_ DATA CP_OUT OPA_IN 7 8 OPA_IP OPA_OUT STATUS_ LOCK GND GND GND GND C I_REF GND AVCC

Contextual Info: HSP43168 Configured to Perform Multi-Channel Filtering Application Note May 1998 AN9421.2 Introduction [ /Title AN94 21 /Subject (HSP4 3168 Configured to Perform MultiChannel Filtering) /Autho r () /Keywords (Intersil Corporation, semiconductor) /Cre- In digital signal processing and communication systems,

71m6542

Abstract: 71M6541 71M654X sm 6415 a-4 s ups transformer winding formula DIODE S4 2G 00x46 Ir sensor 2pin details teridian
Contextual Info: 19-5376; Rev 2; 11/11 71M6541D/F/G and 71M6542F/G Energy Meter ICs DATA SHEET GENERAL DESCRIPTION FEATURES The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature

Contextual Info: M ARRIS S 3x3 10-Bit Convolver Using the HSP43168 Som lconductor T e c h n ic a l B rie f F e b r u a r y 1996 Introduction Theory of Operation The Harris HSP48908 2-D convolver has gained acceptance among customers as an excellent choice for implementing

sm 6415 a-4 s

Abstract: 71M6541 71M654x software user guide 71M6541D 71M6xxx 71m6541f ansi C12.20 71M654X 10 pin flyback transformer schematics "Photo Detector"
Contextual Info: 19-5376; Rev 1.1; 4/11 71M6541D/71M6541F/71M6542F Energy Meter ICs A Maxim Integrated Products Brand DATA SHEET April 2011 GENERAL DESCRIPTION FEATURES The 71M6541D/71M6541F/71M6542F are Teridian’s 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core,

sony ps3 eye camera

Abstract: 6d40 engine diagram sgx530* vector graphics manual dsi CVBS BTA 16 6008 PowerVR SGX series 5 "cmos camera "mc 7258 wiring diagram ccd camera mc 7218 wiring diagram ET 439 power module fuji
Contextual Info: Public Version AR Y OMAP OMAP34xx Multimedia Device Silicon Revision 3.1, 3.1.1 Texas Instruments OMAP™ Family of Products EL IM IN Version R PR Technical Reference Manual Literature Number: SWPU114R July 2007 – Revised April 2009 Public Version www.ti.com

ina328

Abstract: HSP43168 HSP43168JC-33 HSP43168VC-45 Q100 INA822
Contextual Info: HSP43168 Data Sheet July 2004 Dual FIR Filter FN2808.10 configuration of the device is controlled through a standard microprocessor interface. The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16

Contextual Info: LF43168 Dual 8-Tap FIR Filter D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 66 MHz Data and Computation Rate □ Two Independent 8-Tap or Single 16-Tap FIR Filters □ □ □ □ 10-bit Data and Coefficient Inputs 32 Programmable Coefficient Sets

Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685I − DECEMBER 2002 − REVISED APRIL 2006 D High Performance 1:5 PLL Clock D D D CTRL_ CLK CTRL_ DATA CP_OUT OPA_IN 7 8 OPA_IP OPA_OUT STATUS_ LOCK GND GND GND GND C I_REF GND AVCC

SOURCE CODE FOR DIGITAL WEIGHT SCALE

Abstract: Rogowski Coil G-001 sensor 43a ads131e08 spwh
Contextual Info: ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561 – JUNE 2012 Analog Front-End for Power Monitoring, Control, and Protection Check for Samples: ADS131E04, ADS131E06 , ADS131E08 FEATURES 1 • • 23 • • • • • • • • Eight Differential Current and Voltage Inputs

MUX21

Contextual Info: CDC7005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER SCAS685A – DECEMBER 2002 – REVISED FEBRUARY 2003 D High Performance 1:5 PLL Clock TERMINAL ASSIGNMENTS TOP VIEW Synchronizer D Two Clock Inputs: VCXO_IN Clock Is D D D D D D D D D D

MUX21

Abstract: CDC7005
Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685D − DECEMBER 2002 − REVISED AUGUST 2004 D High Performance 1:5 PLL Clock D D D D D D D D D D D D D D D Synchronizer Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock

Contextual Info: HSP43168 HARRIS S E M I C O N D U C T O R Dual FIR Filter December 1996 Features Description • Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16