MM74C Search Results

AN-90

Abstract: C1995 J16A MM54C165 MM54C165J MM54C165N MM74C165 MM74C165J MM74C165N
Contextual Info: MM54C165 MM74C165 Parallel-Load 8-Bit Shift Register General Description Features The MM54C165 MM74C165 functions as an 8-bit parallelload serial shift register Data is loaded into the register independent of the state of the clock s when PARALLEL LOAD (PL) is low Shifting is inhibited as long as PL is low

MM74C74J

Abstract: AN-90 C1995 J14A MM54C74 MM54C74J MM54C74N MM74C74 MM74C74N VCCe10V
Contextual Info: MM54C74 MM74C74 Dual D Flip-Flop General Description The MM54C74 MM74C74 dual D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors Each flipflop has independent data preset clear and clock inputs

Contextual Info: MM54C32,MM74C32 MM54C32 MM74C32 Quad 2-Input OR Gate Literature Number: SNOS332A MM54C32 MM74C32 Quad 2-Input OR Gate General Description Features Employing complementary MOS CMOS transistors to achieve low power and high noise margin these gates provide the basic functions used in the implementation of digital

MM74C909N

Abstract: MM74C909 J14A MM54C909J MM54C909N MM74C909J N14A MM54C909
Contextual Info: MM54C909/MM74C909 YjWANational Ju t Semiconductor MM54C909/MM74C909 Quad Comparator General Description Features The MM54C909/MM74C909 co n tain s four independent bipolar voltage com parators designed to operate from standard 54C/74C power su p p lie s. Th e output allo w s

MM74C912N

Abstract: MM74C912 3.5 digit 7 segment display 28 pin configuration "write only memory" N28B bcd 1 digit 7 segment display pin configuration 4 digit 7 segment decoder DS005916
Contextual Info: Revised January 1999 MM74C912 6-Digit BCD Display Controller/Driver General Description The MM74C912 display controllers are interface elements, with memory, that drive a 6-digit, 8-segment LED display. The display controllers receive data information through 5

MM54C154

Abstract: 5893 mm54c154/mm74c154 AN-90 C1995 J24A MM54C154J MM54C154N MM74C154 MM74C154J
Contextual Info: MM54C154 MM74C154 4-Line to 16-Line Decoder Demultiplexer General Description Features The MM54C154 MM74C154 one of sixteen decoder is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors The device is provided with two strobe inputs both of

MM74C157N

Abstract: 5894 AN-90 C1995 J16A MM54C157 MM54C157J MM54C157N MM74C157 MM74C157J
Contextual Info: MM54C157 MM74C157 Quad 2-Input Multiplexers General Description Features These multiplexers are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement transistors They consist of four 2-input multiplexers with common select and enable inputs When

Contextual Info: Sem iconductor MM54C00/MM74C00 MM54C02/MM74C02 MM54C04/MM74C04 MM54C10/MM74C10 MM54C20/MM74C20 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter Triple 3-Input NAND Gate Dual 4-Input NAND Gate General Description Features These logic gates employ complementary MOS CMOS to

AN-90

Abstract: C1995 J16A MM54C195 MM54C195J MM54C195N MM74C195 MM74C195J MM74C195N TL 5902
Contextual Info: MM54C195 MM74C195 4-Bit Registers General Description Features The MM54C195 MM74C195 CMOS 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear The following two modes of operation are possible

MM74C173N

Abstract: AN-90 C1995 J16A MM54C173 MM54C173J MM54C173N MM74C173 MM74C173J
Contextual Info: MM54C173 MM74C173 TRI-STATE Quad D Flip-Flop General Description Features The MM54C173 MM74C173 TRI-STATE quad D flip-flop is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors The four D-type flip-flops operate synchronously from a

MM74C48N

Abstract: BCD-TO-7-SEGMENT DECODER 11 pin 7 segment filament MM74C48 MS-001 N16E
Contextual Info: Revised January 1999 MM74C48 BCD-to-7 Segment Decoder General Description Features The MM74C48 BCD-to-7 segment decoder is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Seven NAND gates and one driver are connected in pairs

4 BIT 2 INPUT MULTIPLEXER

Abstract: 74VHC4053 8 bit wide 2 to 1 multiplexer multiplexer 74F151A CMOS Multiplexer 4 output multiplexer low power demultiplexer DIGITAL MULTIPLEXER ttl multiplexer
Contextual Info: Logic Products by Function Multiplexer Products Logic Product Family Product Description Package Voltage Node MM82C19 74C CMOS 16-Line to 1-Line Multiplexer DIP 5 other DM74150 Bipolar-TTL Data Selector/Multiplexer DIP 5 MM74C150 74C CMOS 16-Line to 1-Line Multiplexer 3-STATE

74C76

Contextual Info: O ctober 1987 Revised Ja nuary 1999 SEMICONDUCTOR!!^ MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset General Description Features The M M 74C 73 and M M 74C 76 dual J-K flip-flops are m ono­ lithic com plem entary MOS CMOS integrated circuits con­

Contextual Info: s e m ic o n d u c t o r Revised Ja nuary 1999 MM74C89 64-Bit 3-STATE Random Access Read/Write Memory General Description A ddress O peration: Address inputs must be stable tsA prior to the positive to negative transition of m em ory enable. It is thus not necessary to hold address inform ation

74C914N

Contextual Info: O ctober 1987 Revised Ja nuary 1999 SEMICONDUCTOR!!^ MM74C914 Hex Schmitt Trigger with Extended Input Voltage General Description typ 0.0005V /°C at V qq = 10V . And the hysteresis, V j + - The M M 74C 914 is a m onolithic C M O S Hex S chm itt trig ge r

74C902

Abstract: 74c901n
Contextual Info: s e m ic o n d u c t o r Revised Ja nuary 1999 MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL Buffer Features • W ide supply voltage range: 3.0V to 15V ■ G uaranteed noise m argin: 1.0V ■ High noise im m unity: V qq ■ T T L com patibility:

74C906N

Abstract: 74c907n
Contextual Info: O ctober 1987 Revised Ja nuary 1999 SEMICONDUCTOR!!^ MM74C906 • MM74C907 Hex Open Drain N-Channel Buffers Hex Open Drain P-Channel Buffers General Description All inputs are protected from static discharge by diode clam ps to V qq and to ground. The M M 74C 906 and M M 74C 907 buffers em ploy m onolithic

NSB3881

Abstract: NSB5881 INS8060 74C911 NSA1298 NSN581 MICROPROCESSOR Z80 7segment 4-DIGIT 7-SEGMENT LED DISPLAY datasheet MULTIPLEX MM2114 NSB7881
Contextual Info: Fairchild Semiconductor Application Note 257 May 1981 I. INTRODUCTION The MM74C911, MM74C912 and MM74C917 are CMOS display controllers that control multiplexing of 8-segment LED displays. These devices each have an on-chip multiplex oscillator and associated logic to easily implement multi-digit

Contextual Info: March 1988 MM54C89/MM74C89 64-Bit TRI-STATE Random Access Read/W rite Memory General Description The MM54C89/MM74C89 is a 16-word by 4-bit random ac­ cess read/write memory. Inputs to the memory consist of four address lines, four data input lines, a write enable line

74C192

Abstract: 74C221 74c901 74C902 74c904 80c95 HD-74C175 HD-74C174 ttl buffer 74C174
Contextual Info: FUNCTION HARRIS NATIONAL TELEDYN E Three State Quad D F lip -F lo p H D -7 4 C 1 73 MM74C173 MM74C173 Hex D Flip -F lo p H D -74C174 MM74C174 Quad D F lip -F lo p H D -74C175 MM74C175 Synchronous 4-Bit Up/ Down Decade Counter H D -74C192 MM74C192 MM74C192

74c373

Abstract: M74C373N 74c374 M74C374
Contextual Info: Revised January 1999 SEMICONDUCTOR TM MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop General Description The M M 74C 373 and M M 74C 374 are integrated, com ple­ m entary MOS C M O S , 8-bit storage elem ents with 3STATE outputs. These outputs have been specially

Contextual Info: O ctober 1987 Revised January 1999 SEMICONDUCTOR TM MM74C85 4-Bit Magnitude Comparator General Description V|N (i applied to the A = B input and low level voltage (V|N(o) applied to A > B and A < B inputs. Features • W ide supply voltage range: ■ Guaranteed noise m argin:

74C193N

Abstract: 74C192N 74C192
Contextual Info: 1 Q Q Q Revised O ctober 1999 SEMICONDUCTOR TM MM74C192 • MM74C193 Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary Counter General Description Features The M M 74C 192 and M M 74C 193 up/down counters are m onolithic com plem entary M OS CM OS integrated cir­

74LS86 fan in

Abstract: fan out of ic 74ls86 74c863
Contextual Info: O ctober 1987 Revised January 1999 S E M I C O N D U C T O R TM MM74C86 Quad 2-Input EXCLUSIVE-OR Gate General Description Features The M M 74C 86 em ploys co m plem entary MOS CMOS transistors to achieve w ide pow er supply operating range, low pow er consum ption and high noise m argin these gates