MK2015 Search Results

Contextual Info: BACK MK2015 PECL Clock Synthesizer ICROCLOCK Description Features The MK2015 is an inexpensive way to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the device uses a standard

USB connector DIAGRAM

Abstract: homepna chipset usb port diagram on motherboard 9 pin connector to usb pc motherboard schematics
Contextual Info: RP355 Product Brief Integrated Access Device Reference Design HDWXU WXUHV /LVW Advance Information* ‹ Comprehensive software solution from Wind River Systems ‹ RC32355 integrated processor operating up to 150MHz – 8kB instruction cache – 2kB data cache

transistor k 525

Abstract: k1539 MAN09 K1643 G1 TRANSISTOR mk1407 ICS525-04 K 644 resistor 4.7 k transistor CD 910
Contextual Info: Designing the Output Network for Current Mode Outputs I C R O C LOC K Microclock Applications Note MAN09 Introduction The ICS/MicroClock family of differential clock output devices offer a low cost, low jitter solution for providing differential PECL, ECL, or LVDS clocks at frequencies