MIPS BUS ARCHITECTURE Search Results

cga motorola

Abstract: PowerPC755 PC755B 2138F CBGA360 MPC7400 PC745 PC755 PCX755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

2138F

Abstract: CBGA360 MPC7400 PC745 PC755 ATMEL 745 PCX755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

hall sensor u18 032

Abstract: CBGA360 MPC7400 PC745B PC755B CBGA-255 atmel 0820 PowerPC755B
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755B 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745B) 733 MIPS at 400 MHz (PC755B) at 641 MIPS at 350 MHz (PC745B) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

80960SA

Abstract: 80960SB 65A176 AD427
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache

Contextual Info: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins

VAX-11

Abstract: PLCC 68 intel package dimensions 270917 w1a31 intel core i7 processors their registers in term of 32-bit mode
Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

cga motorola

Abstract: CBGA360 MPC7400 PC745 PC755 N-19 CI-CGA360 PowerPC755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

ATMEL 745

Abstract: PCX755 PC755B CBGA360 MPC7400 PC745 PC755 PCX745 PC745 PBGA255 C PBGA255
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

cga motorola

Abstract: PCX755B IEC C13 pinout Tag 225 600 replacement PC745B PC755B MPC7400 PowerPC755B PC755 20d100
Contextual Info: Features H H H H H H H H H H H H H H H 18.1SPECint95, estimates 12.3 SPECfp95 @400Mhz PC755B 15.7SPECint95, 9SPECfp95 @350Mhz (PC745B) 733 MIPS @ 400Mhz (PC755B) et 641 MIPS@350Mhz (PC745B) Selectable bus clock (12 CPU bus dividers up to 10x) PD typical 6,4W @ 400Mhz, full operating conditions.

PBGA255

Abstract: 25X25 PowerPC755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

T7 DIODE

Contextual Info: inttJ PBßyiiflOMÄlHV 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

QFP PACKAGE thermal resistance

Abstract: 80960SA 80960SB N80960SB1 65A176 AD928
Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache

QFP PACKAGE thermal resistance

Abstract: 65a176 AD427 80960SA 80960SB x80960SB 272207 D010D
Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache

Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

Contextual Info: V320USC Universal System Controller PCI System Controller for 32-Bit MIPS and SuperH™ System Interface • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus • Programmable chip select / peripheral device

Contextual Info: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Overview • Glueless interface between popular MIPS and SuperH processors and the standard 32-bit PCI bus

Contextual Info: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Overview • Glueless interface between popular MIPS and SuperH processors and the standard 32-bit PCI bus

V320USC

Contextual Info: V320USC HIGH INTEGRATION, LOW COST PCI SYSTEM CONTROLLER For 32 Bit MIPS and SuperH™ Processors ▼ Glueless interface between the popular MIPS™ and SuperH™ processors and the industry standard PCI Bus ▼ Fully compliant with PCI 2.2 specification

Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • ■ ■ High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

bcm1125h

Abstract: DDR PHY ASIC BCM5461 TSMC Flash BCM1122 BCM1250 MIPS64
Contextual Info: BCM1122 HIGH-PERFORMANCE MIPS CONTROL PROCESSOR SUMMARY OF BENEFITS FEATURES • 400 MHz MIPS64 CPU • Industry-leading performance • 2.2 Dhrystone MIPS/MHz • 51-Gbps on-chip bus bandwidth, 13-Gbps memory bandwidth • Low power dissipation at 4W

BCM1122

Abstract: MIPS64 DDR PHY ASIC BCM1125H BCM1250 BCM5461 bcm546 DSLAM ALU
Contextual Info: BCM1122 HIGH-PERFORMANCE MIPS CONTROL PROCESSOR SUMMARY OF BENEFITS FEATURES • 400-MHz MIPS64 CPU • Industry-leading performance • 2.2 Dhrystone MIPS/MHz • 51-Gbps on-chip bus bandwidth, 13-Gbps memory bandwidth • Low power dissipation at 4W