MIPS 16-BIT BUS ARCHITECTURE Search Results

Contextual Info: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins

QFP PACKAGE thermal resistance

Abstract: 80960SA 80960SB N80960SB1 65A176 AD928
Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache

n80960sb

Contextual Info: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins

QFP PACKAGE thermal resistance

Abstract: 65a176 AD427 80960SA 80960SB x80960SB 272207 D010D
Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache

Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

Contextual Info: in te i 80960SA/80960SB EMBEDDED 32-BIT PROCESSORS WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS Burst Execution at 16 MHz — 5 MIPS* Sustained Execution at 16 MHz Built-In Interrupt Controller — 4 Direct Interrupt Pins — 32 Priority Levels 256 Vectors

VAX-11

Abstract: 272207
Contextual Info: in t t J P ß m oM ow A nv 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

80960SA

Abstract: 80960SB 65A176 AD427
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache

VAX-11

Abstract: PLCC 68 intel package dimensions 270917 w1a31 intel core i7 processors their registers in term of 32-bit mode
Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

T7 DIODE

Contextual Info: inttJ PBßyiiflOMÄlHV 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • ■ ■ High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

80960SA

Abstract: 80960SB 65A176 272206-003
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

AT91M40400

Abstract: 25ac M4040025
Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb Processor - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation • 4K Bytes Internal RAM • Fully Programmable External Bus Interface EBI

edi pb10

Abstract: edi pb20
Contextual Info: Features * Utilizes the ARM7TDMI ARM Thumb® Processor - High-performance 32-bit RISC architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation * 2/8K bytes Internal RAM * Fully programmable External Bus Interface (EBI)

AT91M40400

Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb Processor - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation • 4K Bytes Internal RAM • Fully Programmable External Bus Interface EBI

Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb Processor - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation • 4K Bytes Internal RAM • Fully Programmable External Bus Interface EBI

Contextual Info: Features • Incorporates the ARM7TDMI ARM Thumb® Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation • 4K Bytes Internal RAM • Fully Programmable External Bus Interface (EBI)

Contextual Info: QL902M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights 16 KB On-Chip SRAM • Accessible by all AHB bus masters or the FPGA fabric CPU Core • 32-bit MIPS 4Kc processor runs up to 233 MHz (303 Dhrystone MIPS)

Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-Circuit Emulation • 2K Bytes Internal RAM • Fully-program mable External Bus Interface (EBI)

Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor - High-performance 32-bit RISC architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In Circuit Emulation • 2/8K bytes Internal RAM • Fully programmable External Bus Interface (EBI)

adqr

Abstract: LBIT 204 AT91M63200 "32-Bit Microcontroller"
Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-Circuit Emulation • 2K Bytes Internal RAM • Fully-program mable External Bus Interface (EBI)

LDR type orp 12

Abstract: J 292 0 B3 lorb AT91M63200 PA-23s
Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-Circuit Emulation • 2K Bytes Internal RAM • Fully-program mable External Bus Interface (EBI)