MEMORY ARBITRATION SCHEME Search Results

WE VQE 23 F

Abstract: AM2970 Dynamic Memory Refresh Controller WE VQE 11 E WE VQE 24 E hat 901 cs dmc ge AM2968
Contextual Info: 1 . r ,/ Am2970 Dynamic Memory Timing Controller ^T'f v o 1A '-* ' A , PRELIMINARY > 3 to DISTINCTIVE CHARACTERISTICS Internal or external control of refresh Burst up to 512-cycle , distributed, or hidden refresh Memory access/refresh request arbitration

DS1280s

Abstract: dallas ds1280
Contextual Info: DS1280 DS1280 DALLAS SEMICONDUCTOR 3-Wire to Bytewide Converter Chip FEATURES PIN CONNECTIONS • Adapts JEDEC bytewide memory to a 3-wire serial port • Supports 512K bytes of memory • 68-pin version provides arbitration mechanisms for dual port operation

82353

Abstract: intel 82358 82359 82353 intel intel 82353 82358DT
Contextual Info: 82353 ADVANCED DATA PATH • Dual Port Architecture Allows Host to Access Memory without Incurring EISA Arbitration ■ Provides Optimal i486 Burst Performance ■ High Performance, Flexible Memory Support: — Designed as a 16-Bit Slice which Interfaces 16, 32, or 64-Bit Memory

LSSP1

Contextual Info: DS1280 DALLAS SEMICONDUCTOR DS1280 3-Wire to Bytewide Converter Chip FEATURES PIN ASSIGNMENT • Adapts JEDEC bytewide memory to a 3-wire serial port • Supports 512K bytes of memory • 68-pin version provides arbitration mechanisms for dual port operation

1750a

Abstract: BRQ microcontroller IH67 A00B t34l UT1750AR STD-1750A 1750A processor architecture mil-std-1553 uart dma Y52A
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet September 2001 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA)

PCI I/O interface

Abstract: IDT79R4762 R3051 R3052 R3081 R4650 R4700 Orion Bus
Contextual Info: PCI-to-Orion Bus Bridge IDT79R4762 Product Brief Integrated Device Technology, Inc. FEATURES • • • • Interrupt generation capability On-chip DMA controller Programmable memory mapping Host arbiter functions on chip: - 5 master arbitration - Programmable fixed or round-robin priority scheme

dallas ds1280

Abstract: A12B A18B a17b DS1280 A10B A11B A13B DS1280FP-80
Contextual Info: DS1280 DS1280 3-Wire to Bytewide Converter Chip PIN ASSIGNMENT • Adapts JEDEC bytewide memory A2R A1B A1R A0B A0R RST CLK GND VCC DQE CEB CER WEB WER OEB OER FEATURES to a 3-wire serial port • Supports 512K bytes of memory • 68-pin version provides arbitration mechanisms for

B1189

Abstract: mil-std-1750a MME transistor 401 4AX4 MIL-STD-1750 STD-1750A SI T37B t34l UT1750AR
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet November 2000 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA)

sdram controller

Abstract: Single Data Rate SDRAM Memory Controller EP504 I960 PCI AHB DMA memory bandwidth
Contextual Info: Eureka Technology EP504 AHB Bus to SDRAM Controller Product Summary FEATURES • SDRAM controller interfaces directly with AHB Bus and user interface. • Built-in arbitration between two access ports. • Second access port allows memory sharing with user logic devices.

ADSP-TS203S

Abstract: ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory

ADSP-TS201

Abstract: ADSP-TS203S AA241
Contextual Info: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory

ADSP-TS201 SDRAM

Abstract: TigerSHARC DSP Instruction set specification ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

MIL-STD-38510

Abstract: mil-std-1750 T35I XR18 1750a
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet November 2000 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA)

A12B

Abstract: A14B a17b DS1280 A10B A11B A13B DS1280FP-80
Contextual Info: DS1280 DS1280 3-Wire to Bytewide Converter Chip PIN ASSIGNMENT • Adapts JEDEC bytewide memory A2R A1B A1R A0B A0R RST CLK GND VCC DQE CEB CER WEB WER OEB OER FEATURES to a 3-wire serial port • Supports 512K bytes of memory • 68-pin version provides arbitration mechanisms for

Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

393770

Abstract: CY7C037V CY7C056V CY7C057V
Contextual Info: CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM CY7C056V CY7C057V 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static Features • On-Chip arbitration logic • True dual-ported memory cells that allow simultaneous

393770

Abstract: A144 transistor data sheet CY7C037V CY7C056V CY7C057V sem 2005 16 pin CY7C057V-12AXC CY7CO57V-15AXI
Contextual Info: CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM CY7C056V CY7C057V 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static Features • On-Chip arbitration logic • True dual-ported memory cells that allow simultaneous

ADSP-TS203S

Abstract: ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory

smd 03 jb3

Abstract: l3bc
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

MC68452

Abstract: dbrn 68000M motorola 839 motorola 68000
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68452 Bus Arbitration Module The M C68452 is a bipolar asynchronous bus controller which allows multiple local M P U buses to be multiplexed onto a com m on global bus enabling the local buses to share memory, I/O devices,

SMD MARKING CODE A00b

Abstract: mil-std-1750a MARKING CODE A00B MIL-PRF-38510 as3 SMD Transistor MIL-STD-1750 ttl nim marking a00b SMD A009 pir chip
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet May 2003 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA) q Supports MIL-STD-1750A 32-bit floating-point

M-BUS

Abstract: bus arbitration protocol how dsp is used in radar ADSP-21060 ADSP-21062
Contextual Info: Multiprocessing 7.1 7 OVERVIEW The ADSP-2106x includes functionality and features that allow the design of multiprocessing DSP systems. These features include distributed on-chip arbitration for bus mastership and multiprocessor accesses of the internal memory and IOP registers of other ADSP-2106xs. The ADSP-2106x also has

Contextual Info: CY7C056V CY7C057V CY7C037V CY7C038V3.3 V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM CY7C056V CY7C057V 3.3 V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM Features • On-chip arbitration logic ■ True dual-ported memory cells that allow simultaneous

1750A processor architecture

Abstract: SMD MARKING CODE K3 SMD Marking Code 43a t34p t34h
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet May 2003 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA) q Supports MIL-STD-1750A 32-bit floating-point