MEGACORE Search Results

5M80ZT100

Abstract: 5M570ZM100 5M2210ZF256 5M160ZE64 5m240Zt100 5M1270ZF324 5m570ZT144 EP4CE15F17 5M40ZE64A5 5M1270ZT
Contextual Info: The Automotive-Grade Device Handbook The Automotive-Grade Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com AUT5V1-2.0 Document last updated for Altera Complete Design Suite version: Document publication date: 11.0 May 2011 Subscribe 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

BM1S

Abstract: sonet testbench CP155
Contextual Info: SONET/SDH STS-3c/STM-1 Framer MegaCore Function STS3CFRM December 19, 2000; ver. 1.00 Features • ■ ■ ■ ■ ■ ■ Typical Applications Easy-to-use MegaWizard Plug-In generates MegaCore® variants QuartusTM software and OpenCoreTM feature allow place-and-route,

vhdl code for interleaver

Abstract: vhdl code for block interleaver design for block interleaver deinterleaver RE35 umts turbo encoder vhdl code download REED SOLOMON convolutional interleaver Convolutional interleaver by vhdl interleaver time
Contextual Info: Symbol Interleaver/Deinterleaver MegaCore Function User Guide Version 1.2 August 2000 Symbol Interleaver/Deinterleaver MegaCore Function User Guide, August 2000 A-UG-INTERLEAVER-01.2 ACCESS, Altera, AMPP, APEX, APEX 20K, Atlas, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000, FLEX 6000A, MAX, MAX+PLUS,

atm receiver multi bit error header

Abstract: CP155 apex lcd
Contextual Info: ATM Cell Processor 155 Mbps MegaCore Function CP155 June 2001; ver. 1.01 Data Sheet • ■ ■ ■ Features ■ ■ ■ Typical Applications Full-duplex processing capability Up to 155.52 megabits per second (Mbps) transmission rate Easy-to-use MegaWizard Plug-In generates MegaCore® variants

GOERTZEL ALGORITHM VHDL

Abstract: GOERTZEL ALGORITHM verilog GOERTZEL ALGORITHM in vhdl Sliding goertzel algorithm sliding goertzel digital IIR Filter verilog IIR FILTER implementation in c language iir filter applications implementation of fixed point IIR Filter implementing FIR and IIR digital filters
Contextual Info: IIR Compiler MegaCore Function February 2001 User Guide Version 1.0.1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-IIRCOMPILER-1.0.1 IIR MegaCore Function User Guide Altera, APEX, APEX 20K, ByteBlasterMV, MegaCore, OpenCore, and Quartus are trademarks and/or service marks of Altera

8B10B ansi encoder

Abstract: EPF10K30ETC144-1 encoder verilog coding ED8B10B verilog code for fibre channel
Contextual Info: 8b10b Encoder/Decoder MegaCore Function ED8B10B July 2001; ver. 1.01 Introduction Data Sheet Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre Channel, and other applications. The 8b/10b encoder takes byte inputs, and generates a direct current (DC) balanced stream

Contextual Info: T3 Framer MegaCore Function—Implementing Loopback Functions May 2001, ver. 1.00 Introduction Application Note This application note documents the external implementation of loopback functions in a T3 Framer MegaCore Function T3FRM . It covers diagnostic loopback, line loopback, and payload loopback.

A8259

Abstract: interrupt vhdl
Contextual Info: Simulating the a8259 Model June 2000, ver. 1 Introduction with the Visual IP Software User Guide Altera® intellectual property IP MegaCore functions are developed and pre-tested by Altera, and are optimized for specific Altera device architectures. You can test-drive these functions for free via the

design of dma controller using vhdl

Abstract: A8237
Contextual Info: Simulating the a8237 Model June 2000, ver. 1 Introduction with the Visual IP Software User Guide Altera® intellectual property IP MegaCore functions are developed and pre-tested by Altera, and are optimized for specific Altera device architectures. You can test-drive these functions for free via the

Contextual Info: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices AN-617-1.0 Application Note The RapidIO dynamic data rate reconfiguration reference design demonstrates how to use the ALTGX_RECONFIG megafunction to reconfigure the RapidIO MegaCore®

EP4CE15

Abstract: F169 Texas Instruments Cyclone IV EP4C Series Power Reference Designs ep4ce40 CYIV-5V1-1 4CGX75 V-by-One n148 TYPE SKP 38 CL 9001 ep4cgx30f484
Contextual Info: Cyclone IV Device Handbook, Volume 1 Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.6 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

vsim-3373

Contextual Info: SerialLite II MegaCore Function Errata Sheet July 2006, MegaCore Function Version 1.1.0 This document addresses known errata and documentation issues for the SerialLite II MegaCore function version 1.1.0. Errata are functional defects or errors, which may cause the SerialLite II MegaCore function to

Contextual Info: QDRII SRAM Controller MegaCore Function Errata Sheet February 2005, MegaCore Version 1.0.0 Introduction This document addresses known errata and documentation changes for version 1.0.0 of the QDRII SRAM Controller MegaCore Function. Errata are design functional defects or errors. Errata may cause the

ModelSim

Contextual Info: QDRII SRAM Controller MegaCore Function Errata Sheet June 2007, MegaCore Version 7.1 This document addresses known errata and documentation issues for the QDRII SRAM Controller MegaCore function version 7.1. Errata are functional defects or errors, which may cause the QDRII SRAM

vhdl for 8 point fft

Abstract: 8 bit data bus using vhdl Fourier transform EPF10K100
Contextual Info: fft_on_chip Fast Fourier Transform April 1997, ver. 1 Features Functional Specification 7 • ■ ■ ■ ■ General Description Uses the Altera® fft MegaCore function Optimized for the Altera FLEX® 10K device architecture Uses FLEX 10K embedded array blocks EABs to store both data and

digital FIR Filter verilog code

Abstract: verilog code for interpolation filter FIR FILTER implementation in c language FIR Filter matlab verilog code for fir filter FIR filter matlaB design digital FIR Filter VHDL code verilog code for fixed point adder verilog code for linear interpolation filter 16 QAM modulation verilog code
Contextual Info: FIR Compiler MegaCore Function User Guide September 1999 FIR Compiler MegaCore Function User Guide, September 1999 A-UG-FIRCOMPILER-01.10 ACCESS, Altera, AMPP, APEX, APEX 20K, Atlas, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000, FLEX 6000A, MAX, MAX+PLUS, MAX+PLUS II,

21052-AB

Abstract: 430HX 430TX 430VX FF000000
Contextual Info: July 1998, ver. 1.01 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Altera Corporation A-DS-PCIT1-01.01 pcit1 PCI Target MegaCore Function Parameterized pcit1 MegaCore function implementing a 32-bit, 33-MHz peripheral component interconnect PCI target interface

adc controller vhdl code

Abstract: vhdl code for ddr2 vhdl code for sdram controller vhdl code for memory controller ddr2 Designs guide vhdl code for PLL sdram controller DDR2 SDRAM component data sheet vhdl sdram vhdl code for ddr sdram controller
Contextual Info: DDR & DDR2 SDRAM High-Performance Controller Errata Sheet July 2007, MegaCore Version 7.1 SP1 This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM High-Performance Controller MegaCore functions version 7.1 SP1. Errata are functional defects or errors, which

430VX

Abstract: FF000000 21052-AB 430HX 430TX PCIB32 gd-fpc
Contextual Info: 1998年 9 月 ver.1 機能 Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Page 1 A-DS-PCIB-01/J pci_b PCIマスタ／ターゲット MegaCoreファンクション pci_bは32ビット33MHzのペリフェラル・コンポーネント・インタ

matlab

Abstract: simulink PLD-10 matlab simulink
Contextual Info: FIR コンパイラ MegaCoreファンクション Solution Brief 41 June 1999, Ver.1. 01/J ターゲット・アプリケーション： 携帯電話基地局スペクトラム 拡散通信、セット・トップ・ボッ クス、その他のディジタル信号

controller for sdram

Abstract: ddr sdram controller vhdl sdram
Contextual Info: DDR and DDR2 SDRAM HighPerformance Controller Release Notes December 2006, MegaCore Version 6.1 These release notes for the DDR and DDR2 SDRAM High-Performance Controller MegaCore functions version 6.1 contain the following information: • ■ ■ ■ ■

verilog code for CORDIC to generate sine wave

Abstract: verilog code for cordic algorithm vhdl code for cordic vhdl code for rotation cordic CORDIC to generate sine wave fpga verilog code to generate sine wave vhdl code to generate sine wave verilog code for cordic CORDIC to generate sine wave vhdl code for FFT 32 point
Contextual Info: NCO MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

AMD64

Contextual Info: ASI MegaCore Function Release Notes April 2006, MegaCore Version 1.0.0 These release notes for the ASI MegaCore function version 1.0.0 contain the following information: • ■ ■ ■ System Requirements To use the ASI MegaCore function v1.0.0, the following system

vhdl code for 8-bit parity checker

Abstract: vhdl code for 4 channel dma controller vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for parity checker vhdl code for 8-bit parity generator Phoenix Contact 29 61 312 vhdl code download 34h 732 address generator logic vhdl code download
Contextual Info: pci_c MegaCore Function User Guide Version 1.1 June 1999 pci_c MegaCore Function User Guide June 1999 A-UG-PCIC-01.1 P25-04562-00 Altera, BitBlaster, ByteBlaster, ByteBlasterMV, FLEX, FLEX 10K, MegaWizard, MAX, MAX+PLUS, MAX+PLUS II, MegaCore, OpenCore, and specific