MDIO TIMING Search Results

LPC175x

Abstract: MDIO MDIO write MDIO MDC AN10859 AN1085 NXP Interface and Connectivity MDIO controller nxp lpc175x DP83848C
Contextual Info: AN10859 LPC1700 Ethernet MII Management MDIO via software Rev. 01 — 6 August 2009 Application note Document information Info Content Keywords LPC1700, Ethernet, MII, RMII, MIIM, MDIO Abstract This code example demonstrates how to emulate an Ethernet MII

MDIO clause 45 specification

Abstract: cortex read diagram cortex cpu ethernet mdio circuit diagram
Contextual Info: PSoC Creator Component Datasheet MDIO Interface 1.0 Features • MDIO Interface component to be used in conjunction with Ethernet products •    Configurable physical address Supports up to 4.4 MHz in the clock bus mdc Compliant with IEEE 802.3 Clause 45

1000BASE-T2

Abstract: MDIO clause 22 clause 22 phy registers wishbone RD1074 MDIO MDIO controller 3 to 8 bit decoder vhdl IEEE format LCMXO640C-4T100C 100Base-T2
Contextual Info: Accessing Control Registers Through the MDIO Bus February 2010 Reference Design RD1074 Introduction Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface SMI to transfer management data between an Ethernet Media

MDIO

Abstract: ARM926EJ-S C6000 TMS320C6000
Contextual Info: TMS320DM646x DMSoC Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEQ6 December 2007 2 SPRUEQ6 – December 2007 Submit Documentation Feedback Contents Preface. 10

EMAC

Abstract: MDIO C6000 SPRU983 TMS320C6000
Contextual Info: TMS320DM643x DMP Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRU941A April 2007 2 SPRU941A – April 2007 Submit Documentation Feedback Contents Preface. 10

MDIO

Abstract: tms320c64x teardown C6000 TMS320C6000 54923
Contextual Info: TMS320C642x DSP Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEM6A April 2007 2 SPRUEM6A – April 2007 Submit Documentation Feedback Contents Preface. 10

MDIO

Abstract: ARM926EJ-S C6000 TMS320C6000
Contextual Info: TMS320DM644x DMSoC Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUE24A April 2007 2 SPRUE24A – April 2007 Submit Documentation Feedback Contents Preface. 10

10BASET

Abstract: DP83223V DP83846A DP83846AVHG toa25 s558-5999-46
Contextual Info: DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver 2002 National Semiconductor Corporation www.national.com DP83846A RX_CLK RXD[3:0] RX_DV RX_ER CRS COL MDC MDIO TX_EN SERIAL MANAGEMENT TX_ER TX_CLK HARDWARE CONFIGURATION PINS AN_EN, AN0, AN1 (PAUSE_EN)

802.3 CRC32

Abstract: 81313 CRC-32 Gigabit Ethernet PHY MorethanIP ethernet mac 1588 PHY Ethernet to FIFO
Contextual Info: 1588 Tri-Speed Ethernet MAC Core Product Brief V1.0 – March 2006 MAC Receive Application Interface Transmit Application Interface Transmit FIFO Pause Frame Terminate TX Control CRC Gen. Pause Frame Generate Timestamping Configuration Statistics MDIO Master

SPRU401

Abstract: MDIO tms320c64x teardown C6000 SPRU189 SPRU190 TMS320C6000 SPRU628A
Contextual Info: TMS320C6000 DSP Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module Reference Guide Literature Number: SPRU628A March 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

IBM thinkpad r51

Abstract: lcx125 ibm thinkpad board diagram x31 MDIO clause 45 thinkpad r51 ibm thinkpad board x31 ibm thinkpad board diagram a2098 BAV99FSCT-ND PCC2257CT-ND
Contextual Info: SCAN25100 Evaluation Board Manual USER GUIDE June 2006 Interface Division SCAN25100 Evaluation Board User Guide Contents: 1. Introduction Features and Overview 2. Evaluation Board Options Configuration and Control Jumpers MDIO Interface JTAG Interface DDR Parallel Interface

10Gb Ethernet XGXS Core

Abstract: XGXS 8b/10b encoder MDIO MDC MDIO clause 45 ORT42G5 ORT82G5 ba rx
Contextual Info: 10Gb Ethernet XGXS Core July 2003 IP Data Sheet Features • 64-bit data/8-bit control packet generator/checker on the XGMII side that supports standard compliant CRPAT and CJPAT generation and checking for XAUI interoperability testing. • Standard compliant MDIO/MDC interface.

88X2010

Abstract: 88X2040 optical encoder module marvell IEEE 88X2011 88w2
Contextual Info: Transceiver Solutions Alaska X 10 Gigabit Ethernet and 10 Gigabit Fibre Channel LAN/WAN Transceivers 88X2010/88X2011 PRODUCT OVERVIEW MDC MDIO INTn L0_RXP/N L1_RXP/N L2_RXP/N L3_RXP/N L0_TXP/N L1_TXP/N L2_TXP/N L3_TXP/N 8B/10B Decoder FIFO 64B/66B Encoder

PBD14

Abstract: PBD26 PBD24 PBD12 ALLAYER COMMUNICATIONS PBD30 ETD12 PBD18 PBD-28 ETD10
Contextual Info: AL15 Revision 1.0 5-PORT LOW COST 10/100 SWITCH WITH RMII • • • • • • • • Supports five 10/100 Mbit/s Ethernet ports with RMII interface Capable of trunking up to 500 Mbit/s link Full- and half-duplex mode operation Speed auto-negotiation through MDIO

88X2012

Abstract: MARVELL "XAUI to XFI" 10 Gbps phy XFP-10 802.3ae MDIO x-10 transmitter xaui marvell XFP EVALUATION BOARD optical encoder module media converter optical fibre
Contextual Info: Transceiver Solutions Alaska X 10 Gigabit Serial to XGMII Transceiver 88X2012 PRODUCT OVERVIEW TXD[31:0] TXC[3:0] TX_CLK FIFO 64B/66B Encoder Serializer RXD[31:0] RXC[3:0] RX_CLK FIFO 64B/66B Decoder Deserializer TBG/Clock Synthesizer MDC MDIO INTn Management

jabber

Abstract: 23Z128 TNETE2004 TNETX15VEPGE TNETX3150
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

mdio level translator

Abstract: max14595 W80A1 level translator mdio TFL 50 T822CN
Contextual Info: EVALUATION KIT AVAILABLE MAX14595 Low-Power Dual-Channel Logic-Level Translator S Meets Industry Standards General Description  I2C Requirements for Standard, Fast, and High* Speeds  MDIO Open Drain Above 4MHz* The MAX14595 is a dual-channel, bidirectional logiclevel translator designed specifically for low power

Contextual Info: EVALUATION KIT AVAILABLE MAX14595 Low-Power Dual-Channel Logic-Level Translator S Meets Industry Standards General Description  I2C Requirements for Standard, Fast, and High* Speeds  MDIO Open Drain Above 4MHz* The MAX14595 is a dual-channel, bidirectional logiclevel translator designed specifically for low power

Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

M06T

Abstract: 10BaseT-HD filmag
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

PIN assignments of UTP cables

Abstract: 23Z128 TNETE2004 TNETX15VEPGE TNETX3150
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023C – OCTOBER 1996 – REVISED MAY 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

VSC8211

Abstract: RGMII to SGMII PHY SGMII L10M rgmii specification gmii layout 1000BASE-X sfp sgmii RGMII 1000BASE-X SFP/RGMII to SGMII
Contextual Info: ETHERNET PRODUCTS VSC8211 Single Port 10/100/1000BASE-T PHY and 1000BASE-X PHY with SGMII, SerDes, GMII, MII, TBI, RGMII / RTBI MAC Interfaces 3.3v 10/100/1000 Mbps Ethernet MAC 1.2v Cat-5 UTP 10/100/1000BASE-T GMIII / MII, RGMII, TBI, RTBI MDC, MDIO Vitesse VSC8211

VT6103L

Abstract: VT6103X ET901 vt6103 0004H 2001H LQFP-48 "Fast Link Pulse"
Contextual Info: Data Sheet May 9, 2006 ET901 Fast Ethernet Transceiver Features Overview • Single-chip 10Base-T/100Base-TX transceiver. ■ Dual speed: 10/100 Mbits/s. ■ Half-/full-duplex operation. ■ Media-independent interface MII to IEEE 802.3 MAC. ■ MDC/MDIO interface for configuration and status.