MB680 Search Results

XAPP873

Abstract: OSERDES VHDL description for an 8-bit even/odd parity MB86065 IOL13 RAM64X1D RAMB36 Virtex-5 write operation using ram in fpga ML550
Contextual Info: Application Note: Virtex-5 FPGAs R XAPP873 v1.0 May 6, 2008 Virtex-5 FPGA Interface for Fujitsu Digital-to-Analog Converters with LVDS Inputs Author: Marc Defossez Summary This application note describes how to interface a Fujitsu MB86064 digital-to-analog

OSERDES

Abstract: DAC FPGA START KIT Virtex-5 FPGA Packaging and Pinout Specification XAPP873 pcb layout design mobile DDR parallel to serial conversion vhdl RAMB36 iodelay fpga cdma ip vhdl examples ML550
Contextual Info: Application Note: Virtex-5 FPGAs R XAPP873 v1.2 June 15, 2010 Virtex-5 FPGA Interface for Fujitsu Digital-to-Analog Converters with LVDS Inputs Author: Marc Defossez Summary This application note describes how to interface a Fujitsu MB86064 digital-to-analog

OSERDES

Abstract: RAMB36 ML555 MB86064 MB86065 ML550 XAPP873 RAM64X1D iodelay vhdl code for DCM
Contextual Info: Application Note: Virtex-5 FPGAs Virtex-5 FPGA Interface for Fujitsu Digital-to-Analog Converters with LVDS Inputs R XAPP873 v1.1 December 7, 2009 Author: Marc Defossez Summary This application note describes how to interface a Fujitsu MB86064 digital-to-analog

10Gb Ethernet XGXS Core

Abstract: XGXS 8b/10b encoder MDIO MDC MDIO clause 45 ORT42G5 ORT82G5 ba rx
Contextual Info: 10Gb Ethernet XGXS Core July 2003 IP Data Sheet Features • 64-bit data/8-bit control packet generator/checker on the XGMII side that supports standard compliant CRPAT and CJPAT generation and checking for XAUI interoperability testing. • Standard compliant MDIO/MDC interface.

Contextual Info: LINEAR !C 6-CHANNEL 8-BrT A/D CONVERTER MB4053 • DESCRIPTION The Fujitsu MB4053 is 6-channel, 8-bit, single-slope A/D converter subsystem designed to be used in a microprocessor based data control system. This device provides the analog functions while the addressing,