MC100LVEP Search Results

LVEP210

Abstract: MC100 MC100EP210 MC100LVEP210
Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

MC100LVEP14

Abstract: 100 vp14 100VP14
Contextual Info: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or

D1875

Abstract: HVP16 KVP16 LVEL16 MC100LVEP16 MC10LVEP16
Contextual Info: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16

EP11

Abstract: KVP11 MC100LVEP11 MC10LVEP11 930 TSSOP8
Contextual Info: MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for

EP11

Abstract: MC100LVEP11 MC10LVEP11 KU11 930 TSSOP8
Contextual Info: MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for

Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

MC100LVEP14

Abstract: TSSOP-20 MC100LVEP14DTG 0201 footprint
Contextual Info: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or

Contextual Info: MC100LVEP210 2.5V / 3.3VĄ1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single–ended if the VBB output is used. The

100LVEP16

Abstract: KVP16
Contextual Info: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16

vbb vcc vee

Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

MC100

Abstract: MC100EP05 MC100LVEP05
Contextual Info: MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2-input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the

100LVEP34G

Abstract: 6006B2 948F MC100LVEP34 TSSOP-16
Contextual Info: MC100LVEP34 2.5V / 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: MC100LVEP34 2.5V / 3.3VĄECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

HVP16

Abstract: KVP16 LVEL16 MC100LVEP16 MC10LVEP16 2015 soic8
Contextual Info: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver Description MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 8 1 TSSOP−8 DT SUFFIX CASE 948R • 240 ps Propagation Delay • Maximum Frequency > 4 GHz Typical • PECL Mode Operating Range: VCC = 2.375 V to 3.8 V

Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single-ended if the VBB output is

948F

Abstract: 100LVEP34 MC100LVEP34 MC100LVEP34D MC100LVEP34DR2 MC100LVEP34DT MC100LVEP34DTR2
Contextual Info: MC100LVEP34 2.5V / 3.3VĄECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or

LVEP210

Abstract: MC100 MC100EP210 MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2
Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single-ended if the VBB output is

LVEP210

Abstract: MC100 MC100EP210 MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2
Contextual Info: MC100LVEP210 2.5V / 3.3VĄ1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single–ended if the VBB output is used. The

Contextual Info: MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for

QFN-32 footprint

Abstract: MC100LVEP111 qfn32 tray MC100LVEP111FAR2 MC100LVEP111FARG MC100LVEP111MNG MC100LVEP111MNRG LVEP111 MC100LVEP111FA MC100LVEP111FAG
Contextual Info: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or

KVP05

Abstract: ku05 26 MC100 MC100EP05 MC100LVEP05 KU05 MC100LVEP05DTG
Contextual Info: MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With

PIN CONFIGURATION IC 555

Abstract: LQFP-32 footprint QFN-32 footprint lqfp-32 footprint layout LVEP111 MC100 MC100EP111 MC100LVEP111 QFN32 MC100LVEP111FARG
Contextual Info: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or

LVEP111

Abstract: MC100LVEP111FA MC100LVEP111FAR2 MC100 MC100LVEP111
Contextual Info: MC100LVEP111 2.5V / 3.3VĄ1:10 Differential ECL/PECL/HSTL Clock Driver The MC100LVEP111 is a low skew 1–to–10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or