MAX9254 Search Results

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 1; 10/06 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 3; 2/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 4; 7/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 4; 7/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock

MAX9242EUM

Abstract: MAX9242 MAX9246
Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 4; 7/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock

INTRINSIC SAFE CIRCUIT

Abstract: multidrop AN4007 MAX9169 MAX9218 MAX9242 MAX9244 MAX9246 MAX9248 386KB
Contextual Info: Maxim > App Notes > HIGH-SPEED INTERCONNECT Keywords: LVDS, LVDS multiple-drop bus, LVDS Mux, Fail-safe, Common Mode biasing, resistor tolerance, LVDS receiver biasing Feb 23, 2007 APPLICATION NOTE 4007 Robust, Fail-Safe Biasing Circuit for AC-Coupled Multidrop LVDS Bus

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

8133A

Abstract: MAX9209 MAX9213 MAX9220 MAX9236 MAX9242 MAX9244 MAX9246 tekprobe
Contextual Info: Maxim > App Notes > AUTOMOTIVE HIGH-SPEED INTERCONNECT Keywords: skew, margin, RSKM, receiver, deserializer, LVDS, interconnect, strobe signal, inter-symbol interference, ISI, jitter, data, clock, misalignment May 31, 2007 APPLICATION NOTE 4058 Measuring Skew Margin on 4-Channel Deserializers