MASTER SLAVE CLOCK Search Results

marking t92

Abstract: Marking T92 6 PIN TR
Contextual Info: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer

MC10186

Abstract: MC10186FN MC10186L MC10186P
Contextual Info: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer

megafunction

Abstract: EP3SE50 EP3C40-6 EP2C35-6
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Altera Megafunction High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave

MC10176L

Contextual Info: MC10176 Hex D Master/Slave Flip-Flop The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may

MC10176

Abstract: 2T922 MC10176FN MC10176L MC10176P T92 marking
Contextual Info: MC10176 Hex D Master/Slave Flip-Flop The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may

64x18 synchronous sram

Abstract: TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4

verilog code for slave SPI with FPGA

Abstract: XC3S50 XC2V80
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Xilinx Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4

Contextual Info: Ph ilips Sem iconductors l2C slave routines for the 83C751 AN433 Author: Greg Goodhue Presents short and simple l2C software routines that support only slave rather than master or master & slave operation and an A S M demonstration program. The slave-only software in this app note complements the master

DL122

Abstract: MC10186
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Master-Slave Flip-Flop With Reset MC10186 The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive–going

Contextual Info: Atlantic Interface June 2002, ver. 3.0 Functional Specification 13 Features • ■ ■ ■ ■ ■ ■ Functional Description The direction of data flow on the AtlanticTM interface can be either from master to slave master source or slave to master (slave source).

87LPC764

Abstract: AN430 AN435 AN463 AN464 app abstract 87LCP764
Contextual Info: INTEGRATED CIRCUITS ABSTRACT Presents short and simple I2C software routines that support only slave rather than master or master & slave operation and an ASM demonstration program. The slave-only software in this app note complements the master mode software presented in AN464, Using

ST P239

Abstract: 714 p180 verilog code for pci express memory transaction P181 Japan P135 equivalent 714 p181 XC000E HQ240 XC4013EPQ160 XC4013
Contextual Info: PCI Master Interface, PCI Slave Interface February, 1997 Product Description Features • Fully 2.1 PCI compliant 32 bit, 33MHz PCI Interface ◊ Master Initiator/Target , LC-DI-PCIM-C ◊ Slave (Target-only), LC-DI-PCIS-C PCI Master and Slave Interfaces V1.1.0

SP16F70

Contextual Info: A F L E S S E Y W Solid State — - SP16F70 MASTER/SLAVE The SP16F70 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP16F70 relatively insensitive to the shape of the clock waveform, since only the voltage levels at

TRANSISTOR tr4

Abstract: SP1670 SP1670DG SP1670LC TR23 LC20 TR22
Contextual Info: A FLESSEY W S e m ic o n d u c to rs SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at

Contextual Info: QLUX2108-PQ208C Device Data Sheet • • • • • • Utopia Level 2 Slave to Utopia Level 1 Master Bridge 1.0 Utopia Level 2/1 Bridge Core Features • Implements an Utopia L2 Slave and Utopia L1 Master providing a solution to bridge Utopia Level 1 Slave devices to a Level 2 Master

Elcom Technologies

Contextual Info: Synthesized Clock Frequency Translator Series Features Input / Output frequency up to 155.52 / 662.08 / 2488.32 MHz Ultra Low Jitter Generation < 0.25 ps RMS Flat Jitter Transition (< 0.05 dB) LOS Indicator Master and Slave Modes Smooth Transition from Master to Slave

saa 1070

Contextual Info: M M O T O R O L A Military 10586 Hex “D” Master-Slave Flip-Flop with Reset ELECTRICALLY TESTED PER: 5962-8779301 The 10586 contains six high-speed, master slave type “D" flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is

MC1670

Abstract: transistor motorola 359 DL122
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Master-Slave Flip-Flop MC1670 Master slave construction renders the MC1670 relatively insensitive to the shape of the clock waveform, since only the voltage levels at the clock inputs control the transfer of information from data input D to output.

2sa 1303

Abstract: SMD IC ts 3202 BUX 0715
Contextual Info: M M O T O R O L A Military 10576 Hex “D” Master-Slave Flip-Flop ELECTRICALLY TESTED PER: JM 38510/06103 MP0 mini The 10576 contains six high-speed, master slave type “ D" flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is

M 8824

Abstract: m8824 8821 8824 S8824 NS8822 2S H25 88822 D 8821 N8S24
Contextual Info: S IG N E T IC S P R E LIM IN A R Y SPECIFICATIONS DGL I N T E G R A T E D C I RC UI T S 8821 DUAL MASTER-SLAVE J-K BINARY 8822 DUAL MASTER-SLAVE J-K BINARY 8824 DUAL MASTER-SLAVE J-K BINARY The 8821, 8822 a n d 8824 D u a l M aster-Slave J-K B inaries provide pin configuration a n d logic input

SN74ACT2440

Abstract: SN74BCT2420
Contextual Info: SN74ACT2440 NuBus INTERFACE CONTROLLER SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991 • • • • • • • Designed for NuBus Interface Applications Supports Master, Slave, and Master/Slave Applications Conforms to ANSI/IEEE Std 1196-1987

tc4027

Contextual Info: TC4027BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4027BP,TC4027BF TC4027B Dual J-K Master-Slave Flip Flop TC4027B is J-K master-slave flip-flop having RESET and SET functions. In the case of J-K made, when the clock input is given with

AVR32105

Abstract: AP7000 AVR32 AVR32101 STK1000
Contextual Info: AVR32105: Master and Slave SPI Driver Features - Four chip selects with external decoder support allow communication with up to 15 peripherals - Four chip select registers allowing up to four different slave setups in master mode - Supports a wide range of devices

SN74BCT2420

Abstract: SN74ACT2440
Contextual Info: SN74ACT2440 NuBus INTERFACE CONTROLLER SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991 • • • • • • • Designed for NuBus Interface Applications Supports Master, Slave, and Master/Slave Applications Conforms to ANSI/IEEE Std 1196-1987