MASTER SLAVE CLOCK Search Results

marking t92

Abstract: Marking T92 6 PIN TR
Contextual Info: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer

KEIL

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.30 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.10 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.0 Features • Industry-standard NXP® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation  Only two pins SDA and SCL required to interface to I2C bus

MC10186

Abstract: MC10186FN MC10186L MC10186P
Contextual Info: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.20 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.1 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

MC10186

Abstract: MC10186FN MC10186L MC10186P
Contextual Info: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer

Contextual Info: MC10186 Hex D Master-Slave Flip-Flop with Reset The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 2.20 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation    Only two pins SDA and SCL required to interface to I 2C bus

RNW RESISTOR

Abstract: arbitrage verilog code for I2C MASTER
Contextual Info: PSoC Creator Component Data Sheet I2C Master/Multi-Master/Slave 2.10 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation • Only two pins SDA and SCL required to interface to I2C bus

megafunction

Abstract: EP3SE50 EP3C40-6 EP2C35-6
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Altera Megafunction High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave

MOTOROLA 3150

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Master/Slave Flip-Flop The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going

Contextual Info: MOTOROLA MASTER-SLAVE FLIP-FLOP MASTER-SLAVE FLIP-FLOP Master slave construction renders the MC1670 relatively insen­ sitive to the shape o f the clock w aveform, since only the voltage levels at the clock inputs control the transfer of inform ation from

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Master-Slave Flip-Flop With Reset The MC10186 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going

MC10176

Abstract: 2T922 MC10176FN MC10176L MC10176P T92 marking
Contextual Info: MC10176 Hex D Master/Slave Flip-Flop The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may

64x18 synchronous sram

Abstract: TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Master-Slave Flip-Flop With Reset The MC10186 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going

verilog code for slave SPI with FPGA

Abstract: XC3S50 XC2V80
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Xilinx Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4

8XC751

Contextual Info: Philips Semiconductors l2C slave routines for the 83C751 AN433 Author: Greg Goodhue Presents short and simple l2C software routines that support only slave rather than master or master & slave operation and an A S M demonstration program. The slave-only software in this app note complements the master

transistor BC 550

Abstract: TRANSISTOR tr4 SP1670LC
Contextual Info: SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at

SP16F70

Contextual Info: SP16F70 SP16F70 MASTER/SLAVE D TYPE FLIP-FLOP The SP16F70 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP16F70 relatively insensitive to the shape of the clock waveform, since only the voltage levels at

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Master/Slave Flip-Flop MC10176 The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going

d5611

Abstract: MC10176 DL122
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex D Master/Slave Flip-Flop MC10176 The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going