MARKING 2Y SOT26 Search Results
MARKING 2Y SOT26 Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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5962-8950303GC |
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ICM7555M - Dual Marked (ICM7555MTV/883) |
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MG80C186-10/BZA |
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80C186 - Microprocessor, 16-Bit -Dual marked (5962-8850101ZA) |
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54ACT244/B2A |
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54ACT244/B2A - Dual marked (5962-8776001B2A) |
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ICM7555MTV/883 |
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ICM7555MTV/883 - Dual marked (5962-8950303GA) |
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MQ80186-8/BYC |
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80186 - Microprocessor, 16-Bit - Dual marked (8501001YC) |
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MARKING 2Y SOT26 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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74LVC2G06DW-7Contextual Info: 74LVC2G06 DUAL INVERTER WITH OPEN DRAIN OUTPUTS Description Pin Assignments The 74LVC2G06 is a dual inverter gate with open drain outputs. The device is designed for operation with a power SOT26 SOT363 are Future Products supply range of 1.65V to 5.5V. The input is tolerant to 5.5V |
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74LVC2G06 74LVC2G06 OT363 OT26/363 DS35161 74LVC2G06DW-7 | |
Contextual Info: 74LVC2G17 DUAL SCHMITT TRIGGER BUFFER Pin Assignments Description The 74LVC2G17 is a dual Schmitt trigger buffer gate with Top View standard push-pull outputs. The device is designed for (Top View) 1A 1 operation with a power supply range of 1.65V to 5.5V. The |
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74LVC2G17 74LVC2G17 OT363 DS35164 | |
Contextual Info: 74LVC2G17 DUAL SCHMITT TRIGGER BUFFER Description Pin Assignments The 74LVC2G17 is a dual Schmitt trigger buffer gate with Top View standard push-pull outputs. The device is designed for (Top View) 1A 1 operation with a power supply range of 1.65V to 5.5V. The |
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74LVC2G17 74LVC2G17 OT363 DS35164 | |
code z5Contextual Info: 74LVC2G14 DUAL SCHMITT TRIGGER INVERTER Description Pin Assignments The 74LVC2G14 is a dual Schmitt trigger inverter gate with Top View standard push-pull outputs. The device is designed for (Top View) 6 1Y 1A 1 operation with a power supply range of 1.65V to 5.5V. The |
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74LVC2G14 74LVC2G14 OT363 DS35163 code z5 | |
Contextual Info: 74LVC2G17 DUAL SCHMITT TRIGGER BUFFER Description Pin Assignments The 74LVC2G17 is a dual Schmitt trigger buffer gate with standard push-pull outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The SOT26 SOT363 are Future |
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74LVC2G17 74LVC2G17 OT363 OT26/363 DS35164 | |
Contextual Info: 74LVC2G06 DUAL INVERTER WITH OPEN DRAIN OUTPUTS Description Pin Assignments The 74LVC2G06 is a dual inverter gate with open drain Top View outputs. The device is designed for operation with a power (Top View) supply range of 1.65V to 5.5V. The input is tolerant to 5.5V |
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74LVC2G06 74LVC2G06 OT363 DS35161 | |
74LVC2G07Contextual Info: 74LVC2G07 DUAL BUFFERS WITH OPEN DRAIN OUTPUTS Description Pin Assignments The 74LVC2G07 is a dual buffer gate with open drain Top View outputs. The device is designed for operation with a power (Top View) 6 1Y 1A 1 supply range of 1.65V to 5.5V. The input is tolerant to 5.5V |
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74LVC2G07 74LVC2G07 OT363 DS35162 | |
Contextual Info: 74LVC2G14 DUAL SCHMITT TRIGGER INVERTER Pin Assignments Description The 74LVC2G14 is a dual Schmitt trigger inverter gate with Top View standard push-pull outputs. The device is designed for (Top View) 6 1Y 1A 1 operation with a power supply range of 1.65V to 5.5V. The |
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74LVC2G14 74LVC2G14 OT363 DS35163 | |
Contextual Info: 74LVC2G07 DUAL BUFFERS WITH OPEN DRAIN OUTPUTS Pin Assignments Description The 74LVC2G07 is a dual buffer gate with open drain Top View outputs. The device is designed for operation with a power (Top View) 6 1Y 1A 1 supply range of 1.65V to 5.5V. The input is tolerant to 5.5V |
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74LVC2G07 74LVC2G07 OT363 DS35162 | |
dual inverter
Abstract: 74LVC2G04DW-7 Dual Inverter Gate
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74LVC2G04 74LVC2G04 OT363 OT26/363 74LVC2G04. DS35160 dual inverter 74LVC2G04DW-7 Dual Inverter Gate | |
74LVC2G06
Abstract: A115-A C101 DFN1010 marking CL SOT363 marking code sot-26 3.3v
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74LVC2G06 74LVC2G06 OT26/SOT363 DS35161 A115-A C101 DFN1010 marking CL SOT363 marking code sot-26 3.3v | |
Contextual Info: 74LVC2G06 DUAL INVERTER WITH OPEN DRAIN OUTPUTS Description Pin Assignments The 74LVC2G06 is a dual inverter gate with open drain Top View outputs. The device is designed for operation with a power (Top View) supply range of 1.65V to 5.5V. The input is tolerant to 5.5V |
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74LVC2G06 74LVC2G06 DS35161 | |
Contextual Info: 74LVC2G06 DUAL INVERTER WITH OPEN DRAIN OUTPUTS Description Pin Assignments The 74LVC2G06 is a dual inverter gate with open drain Top View outputs. The device is designed for operation with a power (Top View) supply range of 1.65V to 5.5V. The input is tolerant to 5.5V |
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74LVC2G06 74LVC2G06 OT363 DS35161 | |
74LVC2G17
Abstract: A115-A C101 DFN1010 74LVC2G marking CL SOT363
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74LVC2G17 74LVC2G17 OT26/SOT363 DS35164 A115-A C101 DFN1010 74LVC2G marking CL SOT363 | |
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74LVC2G07
Abstract: A115-A C101 DFN1010 marking Z4 marking 52 sot363
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74LVC2G07 74LVC2G07 OT26/SOT363 DS35162 A115-A C101 DFN1010 marking Z4 marking 52 sot363 | |
DFN1010
Abstract: 74LVC2G34 A115-A C101 74LVC2G34W6-7
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74LVC2G34 74LVC2G34 OT26/SOT363 DS35165 DFN1010 A115-A C101 74LVC2G34W6-7 | |
dual inverter
Abstract: "Inverter Gate" 74LVC2G04 A115-A C101 DFN1010 74LVC2G
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74LVC2G04 74LVC2G04 OT26/SOT363 74LVC2G04. DS35160 dual inverter "Inverter Gate" A115-A C101 DFN1010 74LVC2G | |
74LVC2G07Contextual Info: 74LVC2G07 DUAL BUFFERS WITH OPEN DRAIN OUTPUTS Description Pin Assignments Top View The 74LVC2G07 is a dual buffer gate with open drain outputs. The device is designed for operation with a power 1A supply range of 1.65V to 5.5V. The input is tolerant to 5.5V |
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74LVC2G07 74LVC2G07 OT363 OT26/363 DS35162 | |
74lvc2g14
Abstract: cd Schmitt Trigger marking 2Y sot26
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74LVC2G14 74LVC2G14 OT363 OT363 OT26/363 DS35163 cd Schmitt Trigger marking 2Y sot26 | |
74LVC2G34W6-7Contextual Info: 74LVC2G34 DUAL BUFFER Description Pin Assignments Top View The 74LVC2G34 is a dual buffer gate with standard push pull outputs. The device is designed for operation with a 1A power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage |
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74LVC2G34 74LVC2G34 OT363 OT363 OT26/363 DS35165 74LVC2G34W6-7 | |
marking CL SOT363Contextual Info: UNISONIC TECHNOLOGIES CO., LTD U74LVC1G18 Preliminary CMOS IC 1-OF-2 NON-INVERTING DEMULTIPLEXER WITH 3-STATE DESELECTED OUTPUT 4 1 DESCRIPTION The U74LVC1G18 is a 1-of-2 non-inverting demultiplexer with 3-state output. When the select input S is low data passes from A |
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U74LVC1G18 U74LVC1G18 QW-R502-559 marking CL SOT363 | |
SSM3J307T
Abstract: SSM3J328R SSM3J334R
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200-mA BCE0030D SSM3J307T SSM3J328R SSM3J334R | |
Contextual Info: 74LVC2G34 DUAL BUFFER Pin Assignments Description The 74LVC2G34 is a dual buffer gate with standard push pull outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage |
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74LVC2G34 74LVC2G34 DS35165 | |
74LVC2G04W6
Abstract: 74LVC2G04DW-7
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74LVC2G04 74LVC2G04 74LVC2G04. DS35160 74LVC2G04W6 74LVC2G04DW-7 |