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Elite Semiconductor Memory Technology Inc


Elite Semiconductor Memory Technology Inc M14D2561616A-2.5BG DDR2 256Mb 16Mx16 400MHz BGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Karl Kruse GmbH & Co KG	M14D2561616A-2.5BG		100			1 - 10 - 100 - 1000 - 10000 -	Get Quote

M14D2561616A Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: ESM T M14D2561616A DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe DQS, DQS ; DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A	PDF
Contextual Info: ESMT DDR II SDRAM M14D2561616A 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe DQS, DQS ; DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A	PDF
Contextual Info: ESM T M14D2561616A 2L (Preliminary) DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A	PDF
M14D256 Contextual Info: ESMT Preliminary M14D2561616A (2L) DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A M14D256	PDF
Contextual Info: ESMT M14D2561616A 2E DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A	PDF
M14D2561616A Abstract: DDR-533 Contextual Info: ESMT M14D2561616A Operation Temperature Condition TC -40°C~95°C DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle	Original	M14D2561616A M14D2561616A DDR-533	PDF
M14D256 Abstract: ESMT M14D2561616A M14D2561616A DDR2-667 DDR2-800 Contextual Info: ESMT M14D2561616A DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe DQS, /DQS ; /DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A M14D256 ESMT M14D2561616A M14D2561616A DDR2-667 DDR2-800	PDF
Contextual Info: ESMT M14D2561616A 2E Automotive Grade DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A	PDF
Contextual Info: ESM T M14D2561616A Operation Temperature Condition TC -40 C~95 C DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle	Original	M14D2561616A	PDF
Contextual Info: ESMT Preliminary M14D2561616A (2E) DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.	Original	M14D2561616A	PDF