LVDS IP Search Results

Contextual Info: 19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output

MAX9176

Contextual Info: 19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output

Contextual Info: Revised January 2002 FIN1101 LVDS Single Port High Speed Repeater General Description Features This single port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. It accepts and outputs LVDS levels

FIN1101

Abstract: FIN1101K8 FIN1101M M08A high current circuit diagram
Contextual Info: Preliminary Revised September 2001 FIN1101 LVDS Single Port High Speed Repeater Preliminary General Description Features This single port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. It accepts and outputs LVDS levels

Contextual Info: Revised January 2002 FIN1102 LVDS 2 Port High Speed Repeater General Description Features This 2 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The FIN1102 accepts and outputs LVDS levels

Contextual Info: Revised January 2002 FIN1102 LVDS 2 Port High Speed Repeater General Description Features This 2 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The FIN1102 accepts and outputs LVDS levels

Contextual Info: Preliminary Revised January 2002 FIN1104 LVDS 4 Port High Speed Repeater Preliminary General Description Features This 4 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The FIN1104 accepts and outputs LVDS levels

Contextual Info: IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • • IDT5T93GL06 The IDT5T93GL06 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs . The fanout from a differential input to six LVDS

IDT5T93GL02

Contextual Info: IDT5T93GL02 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL02 The IDT5T93GL02 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs . The fanout from a differential input to two LVDS

IDT5T9304

Abstract: IDT5T93GL04
Contextual Info: IDT5T93GL04 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER II General Description Features The IDT5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on

Contextual Info: PTN3460IBS eDP to LVDS bridge for industrial and embedded applications Rev. 1 — 10 September 2014 Product data sheet 1. General description PTN3460IBS is an embedded DisplayPort to LVDS bridge device that enables connectivity between an (embedded) DisplayPort (eDP) source and LVDS display panel.

Contextual Info: LVDS, 1:4 Clock Buffer Terabuffer IDT5T9304I DATA SHEET General Description Features The IDT5T9304I differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver

ADT2T-1T-1P

Abstract: AD9739 AD9739BBCZ docsis 9508g ADCLK914 593 ph 9425 ADT2T INTEL Core i7 860 AVDD33
Contextual Info: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter AD9739 FUNCTIONAL BLOCK DIAGRAM RESET SYNC_IN_P SYNC_IN_N DB0[13:0]P DB0[13:0]N DB1[13:0]P DB1[13:0]N LVDS DRIVER CLOCK DISTRIBUTION SYNCHRONIZER DCI_P DCI_N LVDS DRIVER SYNC_OUT_P SYNC_OUT_N LVDS RECEIVER

IDT5T9304

Contextual Info: LVDS, 1:4 Clock Buffer Terabuffer IDT5T9304 DATA SHEET General Description Features The IDT5T9304 differential clock buffer has a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver

47d15

Abstract: "7 Bit Shift Register" CS5825 DS90CF384 SN75LVDS86 lvds CLK 7xCLK
Contextual Info: Century Semiconductor Inc. CS5825 28:4 LVDS Receiver GENERAL DESCRIPTION FEATURES CS5825 receives four LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output. The clock channel is used for frame sync and fed into

"7 Bit Shift Register"

Abstract: LT1086-3.3 40 pin lvds header CS5821 DS90CF364 SN75LVDS86
Contextual Info: Century Semiconductor Inc. CS5821 21:3 LVDS Receiver GENERAL DESCRIPTION FEATURES CS5821 receives three LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output. The clock channel is used for frame sync and fed into

Contextual Info: 2.5V LVDS, 1:4 Glitchless Clock Buffer TERABUFFER II IDT5T93GL04 NRND DATA SHEET General Description Features The IDT5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver

Contextual Info: 2.5V LVDS, 1:6 Glitchless Clock Buffer TERABUFFER II IDT5T93GL06 NRND DATA SHEET General Description Features The IDT5T93GL06 2.5V differential clock buffer is a user- selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver

IDT5T9306

Abstract: IDT5T93GL06
Contextual Info: 2.5V LVDS, 1:6 Glitchless Clock Buffer IDT5T93GL06 TERABUFFER II DATA SHEET General Description Features The IDT5T93GL06 2.5V differential clock buffer is a user- selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver

IDT5T93GL02

Contextual Info: 2.5V LVDS, 1:2 Glitchless Clock Buffer IDT5T93GL02 TERABUFFER II DATA SHEET General Description Features The IDT5T93GL02 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs. The fanout from a differential input to two LVDS outputs reduces loading on the preceding driver

IDT5T9304

Abstract: IDT5T93GL04
Contextual Info: 2.5V LVDS, 1:4 Glitchless Clock Buffer IDT5T93GL04 TERABUFFER II DATA SHEET General Description Features The IDT5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver

FIN1031

Abstract: FIN1032 FIN1032M FIN1032MTC M16A MTC16
Contextual Info: Revised September 2001 FIN1032 3.3V LVDS 4-Bit High Speed Differential Receiver General Description Features This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels.

Contextual Info: D S90LV001 DS90LV001 800 Mbps LVDS Buffer Texas In s t r u m e n t s Literature Number: SNLS067D £/r Semiconductor DS90LV001 800 Mbps LVDS Buffer General Description An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

Contextual Info: 2.5V LVDS, 1:2 Glitchless Clock Buffer TERABUFFER II IDT5T93GL02 NRND DATA SHEET General Description Features The IDT5T93GL02 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs. The fanout from a differential input to two LVDS outputs reduces loading on the preceding driver