LVDS INPUT Search Results

Contextual Info: DS90LV001 DS90LV001 800 Mbps LVDS Buffer Literature Number: SNLS067D DS90LV001 800 Mbps LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one

MAX9174

Abstract: MAX9174ETB MAX9174EUB MAX9175 MAX9175ETB MAX9175EUB MAX9176
Contextual Info: 19-2827; Rev 0; 4/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9174 has a fail-safe LVDS input and LVDS outputs. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs

Contextual Info: 19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output

86112A

Abstract: DS90LV001 hp 8133A CB22 DS90LV047A LVDS001EVK SD-22 AN-905 stripline pcb FR4 microstrip stub
Contextual Info: LVDS – LVDS Buffer Evaluation Board LVDS001EVK Revision 1.0 April 2001 LVDS001EVK.DOC The LVDS – LVDS Buffer Evaluation Board The LVDS – LVDS Buffer Evaluation Board is used to demonstrate the use and performance of the DS90LV001 device. Input LVDS or LVPECL signals or complementary signals from a signal generator can be probed

Contextual Info: LVDS – LVDS Buffer Evaluation Board LVDS001EVK Revision 1.0 April 2001 LVDS001EVK.DOC The LVDS – LVDS Buffer Evaluation Board The LVDS – LVDS Buffer Evaluation Board is used to demonstrate the use and performance of the DS90LV001 device. Input LVDS or LVPECL signals or complementary signals from a signal generator can be probed

MAX9176

Contextual Info: 19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers Features ♦ 1.0ps RMS Jitter (max) at 670MHz The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output

2500TM

Abstract: signal path designer
Contextual Info: DS90LV001 3.3V LVDS-LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or

DS90LV001

Abstract: DS90LV001TLD DS90LV001TM M08A
Contextual Info: DS90LV001 3.3V LVDS-LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or

2500TM

Abstract: signal path designer
Contextual Info: DS90LV001 3.3V LVDS-LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or

DS90LV001

Abstract: DS90LV001TLD DS90LV001TM M08A
Contextual Info: DS90LV001 3.3V LVDS-LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or

HP70004A

Abstract: Signal Path designer HP708
Contextual Info: January 2001 DS90LV001 3.3V LVDS-LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or

SCAN50C400

Abstract: SCAN50C400UT
Contextual Info: BR4004_5GIGV2 1/9/04 1:03 PM Page 1 SCAN50C400-Quad 1.25/2.5/5.0 Gbps backplane SerDes SCLK Channel 1, 2 Bist test pattern PLL LVDS input register F I F O LVDS transmit LVDS input register F I F O LVDS recieve LVDS output register F I F O LVDS transmit Serializer

Contextual Info: DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 800 Mbps LVDS Buffer Check for Samples: DS90LV001 FEATURES DESCRIPTION • • • • • • The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In

LV001

Contextual Info: DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 800 Mbps LVDS Buffer Check for Samples: DS90LV001 FEATURES DESCRIPTION • • • • • • The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In

Contextual Info: DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 800 Mbps LVDS Buffer Check for Samples: DS90LV001 FEATURES DESCRIPTION • • • • • • The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In

M08A

Abstract: DS90LV001 DS90LV001TLD DS90LV001TM
Contextual Info: DS90LV001 800 Mbps LVDS Buffer General Description The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or

LVDS Cable STP

Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666
Contextual Info: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This

40 pin lvds converter

Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666 LVDS SERIALIZER SWITCHING NOISE SUPPRESSION
Contextual Info: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This

Contextual Info: DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input General Description Features The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks. M-LVDS Multipoint LVDS is a new family of bus interface

DS91M125TMA

Abstract: M16A SOIC-16
Contextual Info: DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input General Description Features The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks. M-LVDS Multipoint LVDS is a new family of bus interface

DS90UR124

Abstract: AEC-Q100 DS90C124 DS90C365A DS90UR241 DS99R421 ISO10605 RGB666 300113
Contextual Info: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to FPD-Link II LVDS (Embedded Clock DC-Balanced) Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This

AEC-Q100

Abstract: DS90C124 DS90C365A DS90UR124 DS90UR241 DS99R421 ISO10605 RGB666
Contextual Info: DS99R421 5-43 MHz FPD-Link LVDS 3 Data + 1 Clock to Single Embedded Clock DC-Balanced LVDS Converter General Description Features The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This

Contextual Info: Data Transmission Texas Instruments Incorporated Keep an eye on the LVDS input levels By E.D. Cole, P.E. Application Engineer, Data Transmission Introduction to LVDS input levels Figure 1. An LVDS system Low-voltage differential signaling LVDS systems (see

Contextual Info: August 8, 2008 DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input General Description Features The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks. M-LVDS Multipoint LVDS is a new family of bus interface