LVDS 520 DEMUX Search Results

g17g2

Abstract: G17G-2 1610MHz receiver d3p 22 35v 2SD2391Q DIODE A7N transistor a7n MAX109 MAX109EHF-D G17-G20
Contextual Info: KIT ATION EVALU E L B AVAILA 19-0795; Rev 0; 4/07 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter ADC enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an

Contextual Info: KIT ATION EVALU E L B AVAILA 19-0795; Rev 1; 3/08 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter ADC enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an

SNR1000

Abstract: diode B4P THD300 1610MHz receiver 2SD2391Q A7N transistor DIODE A7N transistor a7n MAX109 MAX109EHF-D
Contextual Info: KIT ATION EVALU E L B AVAILA 19-0795; Rev 1; 3/08 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter ADC enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an

FpBGA "27 x 27"

Abstract: medical software ECP2M ECP25
Contextual Info: l o W - c o s t f p g a s w i t h h i g h - p e r f o r m a n c e F e a t u r e s LatticeECP2/M Family Exceptional Performance – Uncommon Value The LatticeECP2 EConomy Plus 2nd generation and LatticeECP2M™ families, collectively referred to as LatticeECP2/M, redefine the low-cost FPGA category. By

m9845

Abstract: PM5310-BI CHESS PM5316-BI PM5372 PM5372-BI PM7390-BI PMC-1991797 marking PM5316
Contextual Info: CHESS PRELIMINARY CHESS CHIPSET APPLICATION NOTE PMC-1991797 ISSUE 2 PM5372 CHESS USER’S GUIDE CHESS S/UNI- MACH48 PM7390-BI CB924102A M9845 TSE TBS PM5372-BI CB924102A M9845 PM5310-BI CB924102A M9845 ® SPECTRA- ® 155-QUAD PM5315-BI CB924102A M9845

Contextual Info: MCP37231/21-200 MCP37D31/21-200 200 Msps, 16-/14-Bit Low-Power ADC with 8-Channel MUX Features: • Sample Rates: - 200 Msps for single-channel mode - 200 Msps/Number of channel used • SNR with fIN = 15 MHz and -1 dBFS: - >74 dBFS for 200 Msps • SFDR with fIN = 15 MHz and -1 dBFS:

Contextual Info: MCP37231/21-200 MCP37D31/21-200 200 Msps, 16-/14-Bit Low-Power ADC with 8-Channel MUX Features: • Sample Rates: - 200 Msps for single-channel mode - 200 Msps/Number of channel used • SNR with fIN = 15 MHz and -1 dBFS: - >74 dBFS for 200 Msps • SFDR with fIN = 15 MHz and -1 dBFS:

Contextual Info: EV10AS180A Low Power L-Band 10-bit 1.5 GSps ADC ANALOG to DIGITAL CONVERTER Datasheet Main Features • • • • • • • • • • • • • Single Core ADC Architecture with 10-bit Resolution Integrating a Selectable 1:1/2/4 DEMUX 1.5 GSps Guaranteed Conversion Rate

QSH-030-01-L-D-A

Abstract: InGaAs apd photodiode QTH-030-01-L-D-A l342 samtec QSH-030-01-L-D QSH-030-01-L-D L-342 samtec connector QSH samtec QTH-030-01-L-D-A oc48 transponder
Contextual Info: V23816-N1018-C342/L342 * 3.3 V, 4-Line LVDS Parallel 2.5 GBd Transponder OC-48 SONET/SDH Long Reach (LR-2) up to 80 km Preliminary Dimensions in mm [inches] V23816-N1018-L342 • • • • • • • • Internal High Voltage APD Bias Laser bias alarm and monitor outputs

Contextual Info: AT84CS001 10-bit 2.2 Gsps 1:4 DMUX Datasheet Features • • • • • • • • • • • • • • High-speed ADC Family Companion Chip Selectable 1:2 or 1:4 DMUX Ratio Power Consumption: 2.7W LVDS Compatible Differential Data and Clock Inputs 100Ω Terminated

Contextual Info: EV10AS180AGS Low Power L-Band 10-bit 1.5 GSps ADC ANALOG to DIGITAL CONVERTER Datasheet Main Features • • • • • • • • • • • • • Single Core ADC Architecture with 10-bit Resolution Integrating a Selectable 1:1/2/4 DEMUX 1.5 GSps Guaranteed Conversion Rate

QTH-030-01-L-D-A

Abstract: InGaAs apd photodiode samtec QTH-030-01-L-D-A QSH-030-01-L-D-A
Contextual Info: Fiber Optics 3.3 V, 4-Line LVDS Parallel 2.5 GBd Transponder OC-48 SONET/SDH Long Reach LR-2 up to 80 km V23816-N1018-C342 V23816-N1018-L342 Preliminary Data Features • Compliant with existing standards • Compact integrated transponder unit with – DFB laser diode transmitter with optoisolator

QD004

Abstract: BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 03.5, February 2008 LatticeECP2/M Family Handbook Table of Contents February 2008 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

lfe2m35se

Abstract: c 4161 10Gb Ethernet PCS Core CHN 816 PICMG 3.5 verilog code for GPS correlator chn 622 circuit drawing for PLC for reed 500 ton injection diode din 4147 h128 transistor datasheet
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.8, July 2010 LatticeECP2/M Family Handbook Table of Contents July 2010 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

sm 4109

Abstract: PR99A QD004 BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 03.7, April 2008 LatticeECP2/M Family Handbook Table of Contents April 2008 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

IDT DATECODE MARKINGS

Abstract: vhdl code for radix-4 fft B14 diode on semiconductor lfe2m35e7fn484c QD004 BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.6, May 2010 LatticeECP2/M Family Handbook Table of Contents May 2010 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

equivalent bc 517

Abstract: c 4237 BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.2, January 2009 LatticeECP2/M Family Handbook Table of Contents January 2009 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

IDT DATECODE MARKINGS

Abstract: 12/24 v dc-dc driver schematic F28-F29 CHN L30 pr77a LFE2M20E-5FN484C CHN 816 BUT16 diode din 4147 DIODE sm dda st r12 KS 21604 L21
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.3, March 2009 LatticeECP2/M Family Handbook Table of Contents March 2009 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

pj 48 diode

Abstract: BUT16 LD48
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 05.1, September 2011 LatticeECP2/M Family Handbook Table of Contents September 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

grid tie inverter schematic

Abstract: LFE2-20E-6F256 QD004 BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.7, June 2010 LatticeECP2/M Family Handbook Table of Contents June 2010 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

prbs pattern generator using vhdl

Abstract: BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.9, April 2011 LatticeECP2/M Family Handbook Table of Contents April 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

EV12AS200

Contextual Info: EV12AS200ZPY ANALOG to DIGITAL CONVERTER 12-bit 1.5 Gsps ADC Datasheet Main Features • Single Core ADC Architecture with 12-bit Resolution Integrating a • • • • • • • • • • • • • • • Selectable 1:1 and 1:2 DEMUX Differential Input Clock AC Coupled

KJ -V20

Abstract: QD004 BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 03.4, December 2007 LatticeECP2/M Family Handbook Table of Contents December 2007 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

Contextual Info: DAC1617D1G0 Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 Product data sheet 1. General description The DAC1617D1G0 is a high-speed 16-bit dual channel Digital-to-Analog Converter DAC with selectable x2, ×4 and ×8 interpolation filters. The device is optimized for