LVDS 31 PIN Search Results

LVDM328

Abstract: LVDM3
Contextual Info: Standard Products UT54LVDM328 Octal 400 Mbps Bus LVDS Repeater Advanced Data Sheet October 31, 2001 FEATURES INTRODUCTION q q q q q q q q q The UT54LVDM328 is an Octal Bus Repeater utilizing Low Voltage Differential Signaling LVDS technology for low power, high speed operation. Data paths are fully differential

Contextual Info: SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER Check for Samples: SN65LV1023A SN65LV1224B FEATURES 1 APPLICATIONS AVCC DVCC DVCC DIN1 32 31 30 29 28 27 26 25 24 1

Contextual Info: SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER Check for Samples: SN65LV1023A SN65LV1224B FEATURES 1 APPLICATIONS AVCC DVCC DVCC DIN1 32 31 30 29 28 27 26 25 24 1

Contextual Info: SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER Check for Samples: SN65LV1023A SN65LV1224B FEATURES 1 APPLICATIONS AVCC DVCC DVCC DIN1 32 31 30 29 28 27 26 25 24 1

Contextual Info: Low Voltage 1:5 Differential LVDS Clock Fanout Buffer MC100ES8014 Product Discontinuance Notice – Last Time Buy Expires on 1/31/2014 Product Preview DATASHEET MC100ES8014 The MC100ES8014 is a HSTL differential clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8014 supports

HDMI TO component cable PINOUT

Abstract: hdmi over cat5 LMH7220 DS15BR400 DS15BR401 DS25BR100 DS25BR110 DS25BR120 DS90LV004 DS90LV804
Contextual Info: 8210 Signal_Path_110 6/18/07 1:31 PM Page 1 SIGNAL PATH designer Tips, tricks, and techniques from the analog signal-path experts No. 110 Feature Article.1-7 Extending the Signal Path Over Data Transmission Lines LVDS Buffers .2 — By Lee Sledjeski, Applications Engineer

Contextual Info: Model: FXO-LC52 SERIES LVDS 5 x 3.2mm 2.5V Oscillator Freq: 0.75 MHz to 1.0GHz Rev.03/31/2008 Features XTREMELY Low Jitter Low Cost XPRESS Delivery Frequency Resolution to six decimal places Stabilities to ± 20 PPM -20 to +70°C or -40 to +85°C operating temperatures

Si530

Abstract: 530AB622M080BGR AN256 JESD22-A114 MIL-STD-883F
Contextual Info: S i 5 3 0 / 5 31 P R E L I M I N A R Y D A TA S H E E T C R Y S TA L O S C I L L A T O R XO (10 M H Z T O 1.4 G H Z ) Features Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options

DS15BR400

Abstract: AN1194 DS15BR400EVK DS15BR401 TQFP-48
Contextual Info: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device

DS15BR400

Abstract: DS15BR400EVK AN-1194 DS15BR401 TQFP-48
Contextual Info: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device

LVDS 30 pin hirose LVDS

Abstract: LVDS 30 pin hirose connector LVDS LVDS 30 pin hirose connector df14 LVDS 26 pin hirose LVDS LVDS connector 30 pin lvds 26 pin OUT03 4164702-10 LVDS connector 26 pin VLCD12
Contextual Info: 4164702-10 LVDS Add On Board The LVDS add-on board of P/N : 4164702-10 designs for single pixel LVDS panel. Mechanical drawing 4164702-10 Connector pin assignment : CN5 – Panel connector: HIROSE DF14-20P-1.25 PIN SYMBOL 1 VLCD 2 VLCD 3 GND 4 GND 5 /OUT00

MAX3867

Abstract: MAX3880 MAX3890 MAX3890ECB
Contextual Info: 19-1498; Rev 1; 12/99 KIT ATION EVALU E L B A AVAIL +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs Features ♦ Single +3.3V Supply The MAX3890 is available in the extended temperature range -40°C to +85°C in a 64-pin TQFP exposed-pad

Contextual Info: 19-1498; Rev 1; 12/99 KIT ATION EVALU E L B A AVAIL +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs Features ♦ Single +3.3V Supply The MAX3890 is available in the extended temperature range -40°C to +85°C in a 64-pin TQFP exposed-pad

Contextual Info: CDCUN1208LP www.ti.com SCAS928 – MAY 2012 400 MHz Low Power 2:8 Fan-Out Buffer with Universal Inputs and Outputs Check for Samples: CDCUN1208LP FEATURES • 1 • • • • 2 Configuration Options via pins or SPI/I C : – Input Type (HCSL, LVDS, LVCMOS)

Contextual Info: LMK01801 www.ti.com SNAS573A – JANUARY 2012 – REVISED APRIL 2013 LMK01801 Dual Clock Divider Buffer Check for Samples: LMK01801 FEATURES TARGET APPLICATIONS • • • 1 2 • • • • • • • Pin Control Mode or MICROWIRE SPI Input and Output Frequency Range 1 kHz to

Contextual Info: LMK01801 www.ti.com SNAS573 – JANUARY 2012 LMK01801 Dual Clock Divider Buffer Check for Samples: LMK01801 FEATURES TARGET APPLICATIONS • • • 1 2 • • • • • • • Pin Control Mode or MICROWIRE SPI Input and Output Frequency Range 1 kHz to

330nF capacitor

Contextual Info: 19-1498; Rev 1; 12/99 KIT ATION EVALU E L B A AVAIL +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs Features ♦ Single +3.3V Supply The MAX3890 is available in the extended temperature range -40°C to +85°C in a 64-pin TQFP exposed-pad

Contextual Info: 19-2913; Rev 0; 8/03 Anything-to-LVDS Dual 2 x 2 Crosspoint Switches Also see the MAX9390/MAX9391 for the crossflow version. Ordering Information TEMP RANGE PIN-PACKAGE MAX9392EHJ PART -40°C to +85°C 32 TQFP MAX9392ETJ* -40°C to +85°C 32 Thin QFN MAX9393EHJ

top mark QA1

Abstract: ICS843S2807 ICS843S2807BY MS-026 Nippon capacitors
Contextual Info: PRELIMINARY ICS843S2807 FEMTOCLOCK CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR • Maximum output frequency: 350MHz VCCO_LVCMOS QA0 VEE QB1 • Crystal input frequency: 25MHz QB0 PIN ASSIGNMENT VCCO_LVCMOS • Five banks of outputs: Bank A: one single-ended QA0 LVCMOS output at: 133MHz

Contextual Info: 19-2829; Rev 1; 7/03 Anything-to-LVDS Dual 2 x 2 Crosspoint Switches Ordering Information TEMP RANGE PIN-PACKAGE MAX9390EHJ PART -40°C to +85°C 32 TQFP MAX9390ETJ* -40°C to +85°C 32 Thin QFN MAX9391EHJ -40°C to +85°C 32 TQFP MAX9391ETJ* -40°C to +85°C

ZL30240

Abstract: ZL30240LDF1 54 mhz crystal oscillator ZL302
Contextual Info: Data Sheet Ordering Information ZL30240LDG1 48 Pin QFN Tray ZL30240LDF1 48 Pin QFN Tape/Reel Matte Tin ZL30240 Dual Channel Precision Universal Clock Generator and NCO -40oC to +85oC Package size: 7 x 7 mm Features Outputs • PLL • • Two independently programmable PLLs with ultra low

Contextual Info: * /1 T e x a s In s t r u m e n t s LMK01801 Dual Clock Divider Buffer 1.0 General Description 3.0 Features The LMK01801 is a very low noise solution for clocking sys­ tems that require distribution and frequency division of preci­ sion clocks. S Pin control mode or MICROWIRE SPI

Contextual Info: LVDS Driver MODULE 8 Lines-SOP 3DLV3108VS1372 Low-voltage differential signaling Driver MODULE 3V Eight Line Drivers, based on Quad Pin Assignment Top View SOP 34 (Pitch : 0.65 mm) Features • • • • • • • • • • • >400 Mbps (200 MHz) switching rates

Contextual Info: CDCUN1208LP www.ti.com SCAS928A – MAY 2012 – REVISED JANUARY 2013 400 MHz Low Power 2:8 Fan-Out Buffer with Universal Inputs and Outputs Check for Samples: CDCUN1208LP FEATURES 1 • • • • • Support PCIE gen1, gen2, gen3 Configuration Options via pins or SPI/I2C :