LVDS 30 PIN Search Results

Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527G – FEBRUARY 2002 – REVISED JANUARY 2005 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527G – FEBRUARY 2002 – REVISED JANUARY 2005 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

SN65LVDS1224

Abstract: LVDS Serializer MO-150 SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023
Contextual Info: SN65LV1023/SN65LV1224† 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527B – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

SN65LVDS1023

Abstract: SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1224
Contextual Info: SN65LV1023/SN65LV1224 www.ti.com SLLS527H – FEBRUARY 2002 – REVISED FEBRUARY 2007 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: DS92LV1023E DS92LV1023E 30-66 MHz 10 Bit Bus LVDS Serializer Literature Number: SNLS187A DS92LV1023E 30-66 MHz 10 Bit Bus LVDS Serializer General Description Features The DS92LV1023E is a 300 to 660 Mb/s serializer for highspeed unidirectional serial data transmission over FR-4

Contextual Info: DS92LV1224 DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer Literature Number: SNLS189 DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer General Description Features The DS92LV1224 is a 300 to 660 Mb/s deserializer for high-speed unidirectional serial data transmission over FR-4

LFCSP-WQ

Abstract: ADN4670 MO-220-WHHD
Contextual Info: Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670 FEATURES Low output skew <30 ps typical Distributes one differential clock input to 10 LVDS clock outputs Programmable—one of two differential clock inputs can be selected (CLK0, CLK1) and individual differential clock

MS-026-BBA

Contextual Info: Data Sheet Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670 FEATURES Low output skew <30 ps typical Distributes one differential clock input to 10 LVDS clock outputs Programmable—one of two differential clock inputs can be selected (CLK0, CLK1) and individual differential clock

Contextual Info: SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 JTAG and at-speed BIST General Description The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The

VTL 10D2

Contextual Info: OBSOLETE October 24, 2011 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 JTAG and at-speed BIST General Description The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921226

Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES APPLICATIONS • • 1 • • • • • • • • Low-Voltage Differential 30-Ω to 55-Ω Line

Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES D Backplane or Cabled Multipoint Data and D Low-Voltage Differential 30-Ω to 55-Ω Line D Cellular Base Stations

Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558B – DECEMBER 2002 – REVISED SEPTEMBER 2005 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES APPLICATIONS • • • • • • • • • • 1 Low-Voltage Differential 30-Ω to 55-Ω Line

Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558B – DECEMBER 2002 – REVISED SEPTEMBER 2005 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES APPLICATIONS • • • • • • • • • • 1 Low-Voltage Differential 30-Ω to 55-Ω Line

SN65MLVD200A

Abstract: SN65MLVD201 SN65MLVD201D SN65MLVD203 SN65MLVD206 SN65MLVD207
Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES APPLICATIONS • • 1 • • • • • • • • Low-Voltage Differential 30-Ω to 55-Ω Line

Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558A – DECEMBER 2002 – JUNE 2003 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES D Backplane or Cabled Multipoint Data and D Low-Voltage Differential 30-Ω to 55-Ω Line D Cellular Base Stations

SN65MLVD200A

Abstract: SN65MLVD201 SN65MLVD201D SN65MLVD203 SN65MLVD206 SN65MLVD207 texas 2151
Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES APPLICATIONS • • 1 • • • • • • • • Low-Voltage Differential 30-Ω to 55-Ω Line

Contextual Info: SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 www.ti.com SLLS558B – DECEMBER 2002 – REVISED SEPTEMBER 2005 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER FEATURES APPLICATIONS • • • • • • • • • • 1 Low-Voltage Differential 30-Ω to 55-Ω Line

Contextual Info: SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER Check for Samples: SN65LV1023A SN65LV1224B FEATURES 1 APPLICATIONS AVCC DVCC DVCC DIN1 32 31 30 29 28 27 26 25 24 1

Contextual Info: PL611-30 Programmable Clock T M FEATURES PAD CONFIGURATION • Advanced programmable PLL design  Very low Jitter and Phase Noise < 40ps Pk -Pk typ.  Supports complementary LVCMOS outputs to drive LVPECL and LVDS inputs.  Output Frequencies: o < 400MHz at 3.3V