LVC38 Search Results

Contextual Info: 3.3V CMOS QUAD 2-INPUT NAND GATE OPEN DRAIN , 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 1.27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages

Contextual Info: LVC38A 3.3V CMOS QUAD 2-INPUT NAND GATE OPEN DRAIN EXTENDED COMMERCIAL TEMPERATURE RANGE LVC38A ADVANCE INFORMATION 3.3V CMOS QUAD 2-INPUT NAND GATE (OPEN DRAIN) WITH 5 VOLT TOLERANT I/O DESCRIPTION FEATURES: – – 0.5 MICRON CMOS Technology

Contextual Info: 3.3V CMOS QUAD 2-INPUT NAND GATE OPEN DRAIN , 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 1,27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages

LVc38

Contextual Info: LVC38A ADVANCE INFORMATION 3.3V CMOS QUAD 2-INPUT NAND GATE OPEN DRAIN WITH 5 VOLT TOLERANT I/O D E S C R IP TIO N FE A T U R E S : - 0.5 MICRON CMOS Technology ESD > 2000V per MlL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)