LVC1G86 Search Results

LVC1G86

Contextual Info: LVC1G86 SINGLE 2ĆINPUT EXCLUSIVEĆOR GATE SCES222M − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D DBV PACKAGE TOP VIEW A D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation

Contextual Info: 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O FE A T U R E S : - LVC1G86A ADVANCE INFORMATION D E S C R IP TIO N : - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0

PicoGate

Abstract: IDT74ALVC1G04 IDT74LVC1G79A IDT74LVC1G86A
Contextual Info: LVC1G86A 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O FEATURES: LVC1G86A ADVANCE INFORMATION DESCRIPTION: – – 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015;

IDT74ALVC1G04

Abstract: IDT74LVC1G79A IDT74LVC1G86A
Contextual Info: LVC1G86A 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O FEATURES: LVC1G86A DESCRIPTION: – – 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package Extended commercial range of - 40°C to +85°C

Contextual Info: LVC1G86 SINGLE 2ĆINPUT EXCLUSIVEĆOR GATE SCES222M − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D DBV PACKAGE TOP VIEW A D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation

Contextual Info: 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package Extended commercial range of - 4 0 ° C to +85°C

Contextual Info: 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O FE A T U R E S : - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 0.65mm pitch PSOP package - Extended commercial range of - 40° C to +85° C

74LVC1G18

Abstract: 5pin L6 inverter cross reference guide 74LVC1G19 SN74AUP1T08 SN74AUP1T02 TC7WZU04 LVC2T45 TC7SZ044 0.3mm pitch csp package
Contextual Info: Little Logic Guide Gate Functions Signal-Switch Functions Configurable Functions Translation Functions > Availability > Quality > Service > Support > Pricing www.ti.com/littlelogic 2011 Little Logic Guide ➔ Table of Contents Overview 3 Little Logic Products by Performance

NXP 74LVC1G

Abstract: SN74LVC2G TC7SZU04 "cross-reference" 74AHC1G14 SOT-23 SCYT129E SN74AUP AUP1G00 74AUP3G17 TC7SG125 nxp Cross-reference
Contextual Info: Little Logic Guide Gates Configurables Signal Switches Translators www.ti.com/littlelogic 2012 Little Logic Guide ➔ Table of Contents Overview 3 Little Logic Products by Performance 4 Logic Migration to 1.8-V Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4