LVC1G08 Search Results

Contextual Info: 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package Extended commercial range of - 4 0 ° C to +85°C

sis m672

Abstract: sis*307elv SiSm672 south bridge SIS 968 SiS307ELV 9LPR600CGLF ICS9LPR600 CLEVO intel meron cpu bu 2508 af equivalent
Contextual Info: Preface Notebook Computer M72XSR Service Manual Preface I Preface Notice The company reserves the right to revise this publication or to change its contents without notice. Information contained herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are

PicoGate

Abstract: S05-1
Contextual Info: 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O D E S C R IP TIO N : FE A T U R E S : - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package Extended commercial range of - 40° C to +85° C

Contextual Info: Product Folder Sample & Buy Technical Documents Support & Community Tools & Software LVC1G08 SCES217Y – APRIL 1999 – REVISED APRIL 2014 LVC1G08 Single 2-Input Positive-AND Gate 1 Features • 1 • • • • • • • • • 3 Description

Contextual Info: LVC1G08 SINGLE 2ĆINPUT POSITIVEĆAND GATE SCES217S − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

Contextual Info: 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package Extended commercial range of - 40°C to +85°C

LVC1G08A

Contextual Info: LVC1G08A 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – – – – – 0.5 MICRON CMOS Technology

Contextual Info: 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O J m ï ï ., D E S C R IP TIO N : FE A T U R E S : - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package

IDT74LVC1G08A

Abstract: IDT74LVC1G08 IDT74ALVC1G04 IDT74LVC1G79A LVC1G08
Contextual Info: LVC1G08A 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS SINGLE 2-INPUT POSITIVE-AND GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – – – – – 0.5 MICRON CMOS Technology

LVC1G08

Contextual Info: LVC1G08 SINGLE 2ĆINPUT POSITIVEĆAND GATE SCES217S − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

74LVC1G18

Abstract: 5pin L6 inverter cross reference guide 74LVC1G19 SN74AUP1T08 SN74AUP1T02 TC7WZU04 LVC2T45 TC7SZ044 0.3mm pitch csp package
Contextual Info: Little Logic Guide Gate Functions Signal-Switch Functions Configurable Functions Translation Functions > Availability > Quality > Service > Support > Pricing www.ti.com/littlelogic 2011 Little Logic Guide ➔ Table of Contents Overview 3 Little Logic Products by Performance

NXP 74LVC1G

Abstract: SN74LVC2G TC7SZU04 "cross-reference" 74AHC1G14 SOT-23 SCYT129E SN74AUP AUP1G00 74AUP3G17 TC7SG125 nxp Cross-reference
Contextual Info: Little Logic Guide Gates Configurables Signal Switches Translators www.ti.com/littlelogic 2012 Little Logic Guide ➔ Table of Contents Overview 3 Little Logic Products by Performance 4 Logic Migration to 1.8-V Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4