LVC16952A Search Results
LVC16952A Datasheets Context Search
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74LVC05
Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
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32-bitcompatibilit-785074lvc057400 datasheet 2-input nand gate+8 | |
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Contextual Info: LVC16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O LVC16952A FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using |
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idt74lvc16952a16-bit250psmil-std-883+1 | |
IDT74LVC16952A
Abstract: LVC16952A SO56-2
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idt74lvc16952a16-bit250psmil-std-883+4 | |
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Contextual Info: LVC16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: LVC16952A DESCRIPTION: • Typical tSK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using |
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idt74lvc16952a16-bit250psmil-std-883+1 | |
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Contextual Info: 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FE A T U R E S : - Typical - ESD > 2000V per MIL-STD-883, Method 3015; - 0.635mm pitch SSOP, 0.50mm pitch TSSOP tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0) |
OCR Scan |
16-bitmil-std-883635mm250ps+3 | |
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Contextual Info: jd t Integrated D evice Technology, li e . 3.3V CMOS 16-BIT REGISTEREDTRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O LVC16952A DESCRIPTION: FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) |
OCR Scan |
16-bitidt74lvc16952a250psmil-std-883+4 | |
IDT74LVC16952A
Abstract: LVC16952A SO56-2
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idt74lvc16952a16-bit250psmil-std-883+4 |