LVC16821A Search Results

d1827

Abstract: IDT74LVC16821A LVC16821A
Contextual Info: LVC16821A 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP, 5 VOLT TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O LVC16821A DESCRIPTION: FEATURES: The LVC16821A 20-bit Flip-Flop is built using advanced dual metal

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

IDT74LVC16821A

Abstract: LVC16821A SO56-2
Contextual Info: LVC16821A 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP, 5 VOLT TOLERANT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE LVC16821A ADVANCE INFORMATION 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: – – – – – – –

Contextual Info: LVC16821A 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP, 5 VOLT TOLERANT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE LVC16821A 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: – – – – – – – – – DESCRIPTION:

Contextual Info: 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUT­ PUTS, 5 VOLT TOLERANT I/O FEATURES: - Typical tsK o (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; - 0.635mm pitch S SO P, 0.50mm pitch T S S O P > 200V using machine model (C = 200pF, R = 0)

IDT74LVC16821A

Abstract: LVC16821A SO56-2
Contextual Info: LVC16821A 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP, 5 VOLT TOLERANT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE LVC16821A 3.3V CMOS 20-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: – – – – – – – – – DESCRIPTION: