LVC112A Search Results

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

LCV112A

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289I – JANUARY 1993 – REVISED MARCH 2002 D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Inputs Accept Voltages to 5.5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

LC112A

Abstract: LVC112A A115-A C101 SN74LVC112A SN74LVC112AD
Contextual Info: LVC112A DUAL NEGATIVEĆEDGEĆTRIGGERED JĆK FLIPĆFLOP WITH CLEAR AND PRESET SCAS289K − JANUARY 1993 − REVISED OCTOBER 2003 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

A115-A

Abstract: C101 SN74LVC112A SN74LVC112AD LC112 CPD14
Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

A115-A

Abstract: C101 SN74LVC112A SN74LVC112AD LC112A
Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289K – JANUARY 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology

Contextual Info: 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP,

Contextual Info: 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP,

LVC112A

Abstract: IDT74LVC112A
Contextual Info: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED ADVANCE J-K FLIP-FLOP WITH CLEAR INFORMATION AND PRESET, 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION:

A115-A

Abstract: C101 SN74LVC112A SN74LVC112AD LC112A
Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J – JANUARY 1993 – REVISED AUGUST 2002 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V

IDT74LVC112A

Abstract: LVC112A
Contextual Info: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: – – 0.5 MICRON CMOS Technology

Contextual Info: 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - DESCRIPTION: 0 .5 M IC R O N C M O S T e c h n o lo g y E S D > 2 0 0 0 V p e r M IL -S T D -8 8 3 , M e th o d 301 5; > 2 0 0 V u s in g m a c h in e m o d e l C = 2 0 0 p F , R = 0

LC112A

Abstract: A115-A C101 SN74LVC112A SN74LVC112AD
Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

8 way flip-flop ic

Abstract: IDT74LVC112A LVC112A
Contextual Info: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: This dual negative-edge-triggered J-K flip-flop is built using advanced

10KACN

Abstract: LVC112A EN-4088Z SN74LVC112AD
Contextual Info: TEXAS INSTRUMENTS Final Notification for the Manufacture of SOIC Narrow Body D and SSOP (DL) in all pin variations to TI Mexico Assembly/Test Facility (TMX) December 3, 1997 Abstract Texas Instruments Standard Linear and Logic (SLL) has completed the move of the SOIC and

Contextual Info: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V