LTXD Search Results

Contextual Info: P—LQFP176—2 4 2 4 —0.50A Unii;: nn LTXD - hO d o + i ^l~ l i * — LO 7MAX JT45555555555555JB5555555 ¡: - 1 O £70, 08 O +1 25, 0±0, 2 o m in

Cx2829

Abstract: ,national semiconductor Linear brief lb-3
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

W78C51

Abstract: W78LE812 W78LE812-24 W78LE812F W78LE812F-24 W78LE812P W78LE812P-24
Contextual Info: W78LE812 8-BIT MICROCONTROLLER 1. GENERAL DESCRIPTION The W78LE812 is an 8-bit microcontroller which can accommodate a wide range of supply voltages with low power consumption. The instruction set for the W78LE812 is fully compatible with the standard 8051. The W78LE812 contains an 8K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bidirectional and bit-addressable I/O ports; an additional 5-bit I/O port P4; three 16-bit timer/counters; a

ATmega32H

Abstract: PV15100 PCIE10 atmel 718 ac chopper ATMEGA64HVE2
Contextual Info: Atmel ATmega32HVE2/ATmega64HVE2 8-bit AVR Microcontroller with Precise Analog Frontend for very Accurate Voltage and Current Measurement PRELIMINARY DATASHEET Features ● Single-package fully-integrated ● High precision analog frontend ● 17bit single-ended voltage-ADC

Contextual Info: Features • High Performance, Low Power AVR 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Contextual Info: Preliminary Data Sheet August 1998 microelectronics group Lucent Technologies Bell Labs Innovations TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger Features Applications • Thirty-two full-duplex, serial time-division multi­ plexed TDM highways.

tms 3874

Abstract: RS8228EBG RS8398 Rockwell framer" Trec Part Numbering System GR
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R S Y S T E M S RS8228 Octal ATM Transmission Convergence PHY Device datasheett PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Advance Information This document contains information on a product under development. The parametric information contains target

Contextual Info: xDSL WAN Ethernet Bridge Controller M B 86976 Package • 144-pin, plastic QFP • FPT-144P-M03 ► Descrip tio n The Fujitsu MB 86976 xDSL WAN Ethernet Bridge Controller is a CMOS VLSI device designed for LAN-WAN bridging applications. It offers a high level of integration that

HD648180W0F6

Abstract: HD648180W0F4 5A/1/PURE 5001h
Contextual Info: HD648180W-MCU Micro Controller Unit • DESCRIPTION The HD648180W is an 8-bit CM OS m icrocontroller in the HD64180 family. Its instruction set is upward-compatible with the HD64180Z, hence with the Z-80. Twelve instruc­ tions (seven types) have been added, bringing the total num ­

20F001N

Abstract: SF1012 valor VALOR SF1012 YCL-20F001N 20f001n ycl diode T35 -4-D6 SF1012 valor ST7032 16PT-004S ycl 20f001n
Contextual Info: 5- &KLS%ULGJH • *OXHOHVVFRQQHFWLRQWRPRVW/$1 FKLSV • 8SWR0ESV6\QF:$1OLQN • 8SWRNESV$V\QF:$1OLQN ZLWKLQWHUQDOEDXGUDWHJHQHUDWRU • DGGUHVV/$1WDEOH • • • • • $785(6 • +LJKSHUIRUPDQFHVLQJOHFKLSIXOO

741d

Abstract: SEG CT 7800 DX522
Contextual Info: TMS320C240, TMS320F240 DSP CONTROLLERS S P R S 04 2- OCTOBER 1996 I H i g h - P e r f o r m a n c e St at i c C M O S T e c h n o l o g y • I n c l u d e s the T 3 2 0 C 2 x L P C o r e C P U S o u r c e C o d e C o m p a t i b l e Wi t h • TM S 3 2 0 C 2 5

cdt 1120

Abstract: TMS370C722 PT/IR P050h
Contextual Info: TMS370Cx2x 8-BIT MICROCONTROLLER SPNS018C-FEBRUARY 1 9 9 3 -REVISED FEBRUARY 1997 FN AND F Z P A CKAG E S TOP VI EW C M O S / E E P R O M / E P R O M T e c h n o l o g i e s on a Single Device - M a s k - R O M D e v i c e s for H i g h - V o l u m e Produ ction

1001d

Contextual Info: CYPRESS PRELIMINARY C Y 7 C 95 4D X ATM HOTLink Transceiver Features technology, functionality, and integration over the field proven CY7B923/933 HOTLink. Second generation HOTLink technology UTOPIA level I and II compatible host bus interface Three-bit Multi-phy address capability built-in

vhdl code for 8 bit ODD parity generator

Abstract: vhdl code for 8-bit calculator vhdl code for 4 bit even parity generator vhdl code for 8 bit parity generator XC4013XL PIN BG256 vhdl code for 8-bit parity generator XC4000XL
Contextual Info: UTOPIA Master CC140f March 23, 1998 Product Specification C ooreEl AllianceCORE Facts MicroSystems CoreEl Microsystems 46750, Fremont Blvd.Suite 208 Fremont, CA -94538 USA. Phone: +1 510-770-2277 Fax: +1 510-770-2288 Email: sales@coreel.com URL: www.coreel.com

Contextual Info: General Features • Single-package High Performance, Low Power AVR 8-bit Microcontroller with LIN • • • • • • Transceiver, 5V Regulator 85mA Current Capability and Watchdog Very Low Current Consumption in Sleep Mode 8Kbytes/16Kbytes Flash Memory for Application Program (Atmel ATA6616/ATA6617)

tk5551

Contextual Info: Features • High Performance, Low Power Atmel AVR 8-bit Microcontroller • Advanced RISC Architecture – 123 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation • Non-volatile Program and Data Memories

Contextual Info: ERICSSON ^ Preliminary July 1997 PBL38812 Voice-switch circuit for Handsfree speakerphone TAM Description The PBL 388 12 contains all the necessary circuitry, amplifiers, detectors, comparators and control functions to implement a high performance, voice-switched,

Contextual Info: LTC2430/LTC2431 20-Bit No Latency ∆ΣTM ADCs with Differential Input and Differential Reference U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Low Supply Current 200µA in Conversion Mode and 4µA in Autosleep Mode Differential Input and Differential Reference

Upn scrambler

Abstract: C165 C166 PEB20570 80386EX 128x8 ram ALCATEL PBX intel 4040 PEB 4165 T PEB22521
Contextual Info: ICs for Communications DSP Embedded Line and Port Interface Controller DELIC-LC PEB 20570 Version 2.3 DELIC-PB PEB 20571 Version 2.3 Preliminary Data Sheet 02.00 DS 2 PEB 20570 PEB 20571 Revision History: Current Version: 02.00 Previous Version: - Page Page

ko 247

Abstract: ATA6617 up 6103 s8 equivalent ATA6616 AVR Studio ata6616 ATA6624 KL15 attiny 40 ATtiny 16 611118
Contextual Info: General Features • Single-package High Performance, Low Power AVR 8-bit Microcontroller with LIN • • • • • • Transceiver, 5V Regulator and Watchdog Very Low Current Consumption in Sleep Mode 8 Kbytes/16 Kbytes Flash Memory for Application Program ATA6616/ATA6617

Contextual Info: ATtiny87/ATtiny167 8-bit AVR Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller DATASHEET Features ● High performance, low power Atmel AVR 8-bit microcontroller ● Advanced RISC architecture ● 123 powerful instructions – most single clock cycle execution

atmega16 software uart

Abstract: ATMEGA32M AT90PWM324 mega32 ATMega16 ATMega32 16845 C code for ATMEGA16 atmega32m1 uart source code TCNT00
Contextual Info: Features • High Performance, Low Power AVR 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • • 1. – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

IAD V2.3

Abstract: DELIC-PB Software Users Manual iomu allegro micro DELIC-LC
Contextual Info: D E L I C - P B S o f t w a r e U se r’ s M an u a l , D S 1 , N o v . 2 00 0 DELIC-PB DSP Embedded Line and Port Interface Controller PEB 20571 Version 2.3 Wi r ed Communications N e v e r s t o p t h i n k i n g . Edition 2000-11-21 Published by Infineon Technologies AG,

RXD26

Abstract: circuit diagram for speed checker for highways
Contextual Info: Advisory June 2003 TTSI4K32T, TTSI2K32T, and TTSI1K16T 4096-Channel, 32-Highway Time-Slot Interchanger Introduction This document describes a technical issue that is known to exist with the device. Issue Version 1 TTSI4K32T, TTSI2K32T, and TTSI1K16T Duty Cycle and Jitter Sensitivity on the CK Pin