LTRA38000 Search Results

loadable counter

Contextual Info: CYPRESS Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: F# CYPRESS Features • Full 3 J V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for

Contextual Info: f? CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • U nparalleled FPGA performance for counters, data path, state machines,

Contextual Info: CYPRESS • Features • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • U nparalleled FPGA performance for counters, data path, state machines,

Contextual Info: T0 CYPRESS F eatures • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input -I- logic cell +• output delays under 7 ns • Unparalleled FPGA performance for

Contextual Info: y CYPRESS Features • Very high speed — Loadable counter frequencies greater than 185 MHz —•Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays under 5.5 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: y CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • U nparalleled FPGA performance for counters, data path, state machines,

Contextual Info: PRELIMINARY CYPRESS Features • • Very high speed — Fast clock s driven from d ed icated in p u ts — G lob al clock s driven from d ed i­ cated in p u ts, an y I/O p in s o r in ter­ nal logic — D ata Path freq u en cies at greater than 200 M H z

antifuse programming technology

Contextual Info: S£. CYPRESS Features • TVue 3 3 V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz ADVANCED INFORMATION Ultra338007 UltraLogic Very High Speed 3.3V 7K Gate CMOS FPGA

Contextual Info: y CYPRESS Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for

7C380

Abstract: H7C3
Contextual Info: PRELIMINARY CYPRESS UltraLogic Very High Speed 7K Gate CMOS FPGA Features — M inimum I o l and • Very high speed — Loadable counter frequencies greater than 185 MHz — Chip-to-chip operating frequencies up to 135 MHz — Input + logic cell + output delays

Contextual Info: > CYPRESS Features • Full 33V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-8-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,